A system, method and apparatus to facilitate data exchange via pointers. For example, in a computing system having a first processor and a second processor that is separate and independent from the first processor, the first processor can run a program configured to use a pointer identifying a virtual memory address having an ID of an object and an offset within the object. The first processor can use the virtual memory address to store data at a memory location in the computing system and/or identify a routine at the memory location for execution by the second processor. After the pointer is communicated from the first processor to the second processor, the second processor can access the same memory location identified by the virtual memory address. The second processor may operate on the data stored at the memory location or load the routine from the memory location for execution.

Systems, methods, apparatuses, and computer-readable media for cryptographic authentication to control access to storage devices. An applet executing on a processor of a contactless card may receive, via a wireless communications interface of the contactless card, a request to access a storage device of the contactless card, where the storage device is in a locked state. The applet may generate a cryptogram based on the request and transmit the cryptogram to a computing device via the wireless communications interface. The applet may receive, from the computing device, an indication specifying that a server decrypted the cryptogram. The applet may transmit, to a controller of the storage device and based on the indication specifying that the server decrypted the cryptogram, an indication specifying to unlock the storage device. The controller may transition the storage device from the locked state to an unlocked state based on the indication received from the applet.

A method includes determining one or more quality attributes for memory cells of a memory device, receiving a memory access request involving data written to at least a portion of the memory cells, and determining whether the memory access request corresponds to a random read operation or a sequential read operation. The method further includes responsive to determining that the memory access request corresponds to a random read operation or responsive to determining that the one or more quality attributes for memory cells are greater than a threshold quality level, or both, selecting a read mode for use in performance of the random read operation and performing the random read operation using the selected read mode.

To selectively use cost, performance, reliability, and security characteristics of storage devices in an appropriate manner. A storage system has a plurality of volumes of which reliability and security levels differ from one another, and a controller of the storage system determines a reliability requirement and a security requirement of a file based on at least one of a type and a content of the file, determines a volume to store the file based on the determination result, and stores the file in the determined volume.

A data storage device comprising a data path and an access controller, wherein: the data path comprises: a data port configured to transmit data between a host computer system and the data storage device, wherein the data storage device is configured to register with the host computer system as a block data storage device; a non-volatile storage medium configured to store user content data; and the access controller is configured to: repeatedly and automatically generate a dynamically changing unlock passcode for unlocking the data storage device; receive a first passcode including, at least, an input passcode provided by a user device external to the data storage device, wherein the input passcode is generated externally to the data storage device and synchronously with the generation of the unlock passcode by the access controller; and provide access to the user content data via the data port in response to the first passcode matching with a second passcode generated by the access controller, wherein the second passcode includes at least the unlock passcode.

Methods and apparatus relating to zero-redundancy tag storage for bucketed allocators are described. In some embodiments, memory stores a memory page. The memory page includes a metadata page and a plurality of slots. The metadata page includes information corresponding to the plurality of slots. Decode circuitry decodes an instruction that includes a source operand. Execution circuitry executes the decoded instruction according to the source operand to load a first tag for a first slot of the plurality of slots in response to a memory access request directed at the first slot of the plurality of slots. The memory access request is allowed to proceed in response to a match between the first tag and a second tag of a pointer of the memory access request. The memory page stores a separate tag in proximity to each of the plurality of slots. Other embodiments are also disclosed and claimed.

A dispatch element interfaces with a host processor and dispatches threads to one or more tiles of a hybrid threading fabric. Data structures in memory to be used by a tile may be identified by a starting address and a size, included as parameters provided by the host. The dispatch element sends a command to a memory interface to transfer the identified data to the tile that will use the data. Thus, when the tile begins processing the thread, the data is already available in local memory of the tile and does not need to be accessed from the memory controller. Data may be transferred by the dispatch element while the tile is performing operations for another thread, increasing the percentage of operations performed by the tile that are performing useful work and reducing the percentage that are merely retrieving data.

The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) to include: simulating to issue a first Joint Test Action Group (JTAG) command through a General-Purpose Input/Output (GPIO) interface (I/F) to the SSD device for stopping a running of a processing unit of a flash controller in the SSD device; simulating to issue a second JTAG command through the GPIO I/F to the SSD device for forcing the SSD device to exit a sleep mode; and simulating to issue a third JTAG command through the GPIO I/F to the SSD device for reading a designated length of data from a static random access memory (SRAM) in the SSD device.

Examples implementations relate to configuration of computational drives. An example computational drive includes a housing to be inserted in a drive bay of a host device, and persistent storage. The computational drive may also include a processor to respond to an insertion of the housing into the drive bay of the host device by configuring the computational drive to operate as a new node of a distributed file system, and connecting the computational drive to the distributed file system as the new node.

A storage system performs storage tiering including a first storage device and a second storage device. The first storage device that stores data, the second storage device that stores data that is stored in the first storage device and elapses for a predetermined period of time. A storage control device that stores data in time series in the second storage device, reads the time-series data at a predetermined timing, and reorganizes the read data for each key to store the reorganized data in the second storage device and read the reorganized data from the second storage device when the data is read by the key.