Methods and systems for division operation are described. A processor can initialize an estimated quotient between the dividend and the divisor separately from a floating-point unit (FPU) pipeline. The processor can implement the FPU pipeline to execute a refinement process that can include at least a first iteration of operations and a second iteration of operations. The refinement process can include, in the first iteration of operations, generating a first unnormalized floating-point value using the initialized estimated quotient. The refinement process can include, in the second iteration of operations, generating a second unnormalized floating-point value using the first unnormalized floating-point value. The processor can determine a final quotient based on the second unnormalized floating-point value.

A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b > a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M - 1 modulo units of the logarithmic tree provide x[0: m]mod d for all m ∈ {1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of log.sub.2 M; and more than M - 2.sup.u of the subset of modulo units are arranged at the maximal delay of log.sub.2 M, where 2.sup.u is the power of 2 immediately smaller than M.

This disclosure represents an improved computer system and process to avoid the consequences of improper conversion of numbers and of rounding errors. This process makes the distinction between exact and inexact decimal floating-point numbers. If the result of a sequence of operation is exact, the user can trust that every decimal digit in the computed result is correct. On the other hand, if the input operands are inexact or the result cannot be computed exactly, a loss of significant digits occurs, and the user is warned of the loss. A novel representation is used for the inexact computed values. An estimate of the absolute error is also part of the representation.

An arithmetic processing device includes: a memory; and a processor coupled to the memory and configured to: store a minimum value of a loss function in a first two-dimensional array; and determine a break position in a quantization process on a basis of a second two-dimensional array that represents the break position in a case where the loss function is minimized in the first two-dimensional array.

Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.

A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0:m]mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ┌log.sub.2 M┐; and more than M−2.sup.u of the subset of modulo units are arranged at the maximal delay of ┌log.sub.2 M┐, where 2.sup.u is the power of 2 immediately smaller than M.

A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b] mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0: m] mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ┌log.sub.2 M┐; and more than M−2.sup.u of the subset of modulo units are arranged at the maximal delay of ┌log.sub.2 M┐, where 2.sup.u is the power of 2 immediately smaller than M.

Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.

Various implementations relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation including a masked decomposition of a polynomial a having n.sub.s arithmetic shares into a high part a.sub.1 and a low part a.sub.0 for lattice-based cryptography in a processor, the instructions, including: performing a rounded Euclidian division of the polynomial a by a base α to compute t.sup.(⋅)A; extracting Boolean shares a.sub.1.sup.(⋅)B from n low bits of t by performing an arithmetic share to Boolean share (A2B) conversion on t.sup.(⋅)A and performing an AND with ζ−1, where ζ=−α.sup.−1 is a power of 2; unmasking a.sub.1 by combining Boolean shares of a.sub.1.sup.(⋅)B; calculating arithmetic shares a.sub.0.sup.(⋅)A of the low part a.sub.0; and performing a cryptographic function using a.sub.1 and a.sub.0.sup.(⋅)A.

A modular operation circuit includes a controller, a modular multiplier and a modular adder. The controller divides a first number into K segments. The modular multiplier performs modular multiplication operations and the modular adder performs modular addition operations to the K segments in (K−1) iterations for deriving a remainder of a division of the first number by a second number.