An operational circuit may include a combiner to combine, based on a request for multiplication of integer numbers different from floating-point numbers, a first integer number and a second integer number. The operational circuit may include a multiplier including first and second ports. A third integer number may be inputted to the first port, and a fourth integer number indicating a combination of the first integer number and the second integer number may inputted to the second port. The operational circuit may include a converter to output, based on a fifth integer number indicating a multiplication of the third integer number and the fourth integer number from a third port of the multiplier, a sixth integer number indicating a multiplication of the first integer number and the third integer number, and a seventh integer number indicating a multiplication of the second integer number and the third integer number.

A non-transitory computer-readable recording medium stores an information processing program for causing a computer to execute processing including: acquiring first data that enables, for each of non-zero elements included in multidimensional tensor data, specification of a combination of a value of the element and an index of each dimension that indicates a position of the element; generating, on the basis of the acquired first data, second data that enables specification of a plurality of groups obtained by grouping each of the combinations such that the combinations with indexes that overlap with each other are included in different groups; and performing, on the basis of the generated second data, matricized tensor times khatri-rao product (MTTKRP) processing by setting each combination of a plurality of combinations included in the group as a target of parallel processing in the MTTKRP processing related to the tensor data.

A modular operation circuit includes a controller, a modular multiplier and a modular adder. The controller divides a first number into K segments. The modular multiplier performs modular multiplication operations and the modular adder performs modular addition operations to the K segments in (K−1) iterations for deriving a remainder of a division of the first number by a second number.

Provided are a method and apparatus for a hardware-based accelerated arithmetic operation on homomorphically encrypted messages. The method of performing hardware-based modular multiplication on homomorphically encrypted messages according to the present invention includes receiving a plurality of homomorphically encrypted messages expressed in a polynomial form and a modulus for modular multiplication, decomposing the modulus into a product of a plurality of disjoint factors through CRT operation, and extracting a divided ciphertext from a plurality of homomorphically encrypted messages based on each of the disjoint factors, performing NTT transformation on each coefficient of the divided ciphertext, performing a pointwise multiplication operation between result values of the NTT transformation, performing INTT transformation on a result value of the pointwise multiplication operation to obtain the divided ciphertext, and merging the divided ciphertext obtained in the performing of the INTT transformation through ICRT operation to generate an output ciphertext.

A product-sum calculation device multiplies first and second floating-point numbers and sequentially adds multiplication results. The device adds a first exponent and a second exponent of the respective floating-point numbers for generating a third exponent, multiplies a first mantissa and a second mantissa of the respective floating-point numbers for generating a third mantissa, sets lower n bits of the third exponent to zero and generates a fourth exponent, shifts the third mantissa to the left by the number of bits indicated by the lower n bits and generated a fourth mantissa, generates an error detection code for each 2.sup.n bits of the fourth mantissa, performs digit alignment of the fourth mantissa and a fifth mantissa and outputs an exponent as a new fifth exponent, and adds the fourth mantissa and the fifth mantissa and outputs an addition result as a new fifth mantissa.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

This application discloses a floating-point number multiplication computation method, an apparatus, and an arithmetic logic unit. The method includes: obtaining a plurality of to-be-computed first-precision floating-point numbers; decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, a second precision of the second-precision floating-point number is lower than a first precision of the first-precision floating-point number; determining various combinations including two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination; and determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination.

The present disclosure relates to a multiplier, a method, an integrated circuit chip, and a computation apparatus for a floating-point computation. The computation apparatus may be included in a combined processing apparatus, which may also include a general interconnection interface and other processing apparatus. The computation apparatus interacts with other processing apparatus to jointly complete computation operations specified by the user. The combined processing apparatus may also include a storage apparatus, which is respectively connected to the computation apparatus and other processing apparatus and is used for storing data of the computation apparatus and other processing apparatus. Solutions of the present disclosure may be widely used in various floating-point data computations

A floating-point operation control method, applied to a chip comprising a multiply accumulator, includes receiving a first selection signal, and controlling an operation circuit in the multiply accumulator corresponding to a floating-point operation mode indicated by the first selection signal. The floating-point operation mode supports a multiply accumulate operation of a floating-point number of a first bit width k.sub.1. The method further includes dividing fractional parts of first and second operands into m first and second suboperands of a second bit width k.sub.2. The second bit width k.sub.2=k.sub.1/m. The method further includes performing a multiplication operation based on the m first and second suboperands to obtain a fractional product, and determining a floating-point number sum based on the fractional product and a third operand.

A digital signal processor (DSP), which may be implemented as a DSP block in a field programmable gate array (FPGA), includes a fracturable multiplier, a fracturable adder and a fracturable variable shifter. Further included is at least one sign-extension block, to provide for normal mode, dual-fracturing mode and quad-fracturing mode.