G06F7/4983

ITERATIVE HYBRID MATRIX MULTIPLIER
20250103678 · 2025-03-27 ·

A hybrid time-shared iterative multiply-accumulate circuit comprises a product storage circuit, a multiply circuit operable to receive a first input value, receive a second input value, produce a product of the first input value and the second input value, and store the product in the product storage circuit, an accumulator storage circuit for storing an accumulated value, and an accumulation switch connecting the product storage circuit to the accumulator storage circuit that is operable to electrically connect the product storage circuit and the accumulator storage circuit in parallel or to electrically disconnect the product storage circuit from the accumulator storage circuit.

CONNECTIVITY IN COARSE GRAINED RECONFIGURABLE ARCHITECTURE
20250156370 · 2025-05-15 ·

A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. The tiles can be arranged in an array or grid and can be communicatively coupled. In an example, the tiles can be arranged in a one-dimensional array and each tile can be coupled to its respective adjacent neighbor tiles using a direct bus coupling. Each tile can be further coupled to at least one non-adjacent neighbor tile that is one tile, or device space, away using a passthrough bus. The passthrough bus can extend through intervening tiles.

Switched capacitor vector-matrix multiplier
12321713 · 2025-06-03 · ·

Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.

NON-LINEAR FUNCTION COMPUTING APPARATUS AND NON-LINEAR FUNCTION COMPUTING METHOD

The present embodiment relates to a computing apparatus for computing an interpolated non-linear activation function for an input. The computing apparatus includes a plurality of unit processing elements (PEs), and each unit PE includes: a multiplier that multiplies the input and an output of an accumulator, an adder that adds the output of the multiplier and a coefficient of the interpolated non-linear activation function; and an accumulator that accumulates and outputs the output of the adder.