An artificial neural network (ANN) system includes a processor, a virtual overflow detection circuit and a data format controller. The processor performs node operations with respect to a plurality of nodes included in each layer of an ANN to obtain a plurality of result values of the node operations and performs a quantization operation on the obtained plurality of result values based on a k-th fixed-point format for a current quantization of the each layer to obtain a plurality of quantization values. The virtual overflow detection circuit generates a virtual overflow information indicating a distribution of valid bit numbers of the obtained plurality of quantization values. The data format controller determines a (k+1)-th fixed-point format for a next quantization of the each layer based on the generated virtual overflow information. An overflow and/or an underflow are prevented efficiently by controlling the fixed-point format using the virtual overflow.

A semiconductor device including a multiplier circuit is provided. A first cell, a second cell, and a first circuit are included. The first cell includes a first transistor. The second cell includes a second transistor. The first circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a first switch.

This disclosure represents an improved computer system and process to avoid the consequences of improper conversion of numbers and of rounding errors. This process makes the distinction between exact and inexact decimal floating-point numbers. If the result of a sequence of operation is exact, the user can trust that every decimal digit in the computed result is correct. On the other hand, if the input operands are inexact or the result cannot be computed exactly, a loss of significant digits occurs, and the user is warned of the loss. A novel representation is used for the inexact computed values. An estimate of the absolute error is also part of the representation.

A processor, a method of operating the processor, and an electronic device including the processor are disclosed. The method includes arranging, in respective input registers, weights and activations having a smaller number of bits than a minimum operation unit of an operator included in the processor, performing a multiplication between values stored in the input registers, storing a result of the multiplication in an output register, and outputting, from the output register, a value in a preset bit range as a result of a dot product between a first vector including the weights and a second vector including the activations.

A method and system for reducing power consumed in processing units when processing units are used to calculate computationally expensive linear functions on a sequence of correlated data. Processing of a new data sample may be performed to consume less power by using results obtained from the processing a previous reference data sample.

A neural processor and a control method of the neural processor are provided. The neural processor includes plurality of processing element groups, wherein each of the processing element groups includes a plurality of processing elements configured to perform a vector operation, an overflow accumulator configured to be engaged by a processing element in which an overflow or underflow occurs from among the plurality of processing elements, and a register configured to store information indicating the processing element as an owner processing element.

Operations may include obtaining input data and separating the input data into a first subset of input data and a second subset of input data, the first subset of input data including positive input data and the second subset of input data including negative input data. The operations may include performing positive computations on the first subset of input data to determine one or more first results and performing negative computations on the second subset of input data to determine one or more second results. The operations may include aggregating the one or more first results and the one or more second results to determine a solution based on the aggregating. The operations may include executing an application using a machine learning model or a deep neural network based on the determined solution.

Execution of a machine instruction in a central processing unit. A perform floating-point operation instruction and a test bit are obtained. If the test bit has a first value, a specified floating-point operation function is performed, and a condition code is set to a value determined by the specified function. If the test bit has a second value, a check is made to determine if the specified function is valid and installed on the machine. If the specified function is valid and installed on the machine, the condition code is set to one code value, and if the specified function is either not valid or not installed on the machine, the condition code is set to a second code value.

The present disclosure describes a mixed signal arithmetic logic unit configured to use a combination of analog processing elements and digital processing elements in a cohesive manner. Depending on the signals and the data received for processing, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize computational results and the performance of the mixed signal arithmetic logic unit.

A method provides for decoding, in a microprocessor, an instruction into data identifying a first register, a second register, an immediate value, and an opcode identifier. The opcode identifier is interpreted as indicating that an arithmetic operation is to be performed on the first register and the second register, and that the microprocessor is to perform a change of control operation in response to the addition of the first register and the second register causing overflow or underflow. The change of control operation is to a location in a program determined based on the immediate value. A processor can be provided with a decoder and other supporting circuitry to implement such method. Overflow/underflow can be checked on word boundaries of a double-word operation.