An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a positive sign stored in the first memory, to the second memory; a step of supplying the first data with a negative sign stored in the second memory, to the third memory; a step of generating second data by adding the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory; and a step of storing the second data in the fourth memory are included. When the second data stored in the fourth memory are all second data with a positive sign or all second data with a negative sign, all the second data stored in the fourth memory are added.

The embodiments herein describe techniques for monitoring guard bits in multi-result vectors generated by a first arithmetic unit in a chain and using side band logic to add or subtract offset values from guard bits in a second, subsequent arithmetic unit in the chain. In this manner, the guard bits can be adjusted on the fly (e.g., without interrupting or terminating the chain) to ensure the guard bits do not overflow. The side band logic can maintain a guard bits overflow value which is then combined with the output vector from the final arithmetic unit in the chain to compensate for adjusting the guard bits at the various arithmetic units in the chain. In this manner, the chain can have any desired length.

Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.

Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.

Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.

A method and apparatus for handling overflow conditions resulting from arithmetic operations involving floating point numbers. An indication is stored as part of a thread's context indicating one of two possible modes for handling overflow conditions. In a first mode, a result of an arithmetic operation is set to the limit representable in the floating point format. In a second mode, a result of an arithmetic operation is set to a NaN.

The embodiments herein describe handling overflow that occurs between different portions of a multi-result vector storing results from performing multiple operations in parallel. Rather than using guard bits to separate the various results in the multi-result vector, the embodiments herein describe using overflow monitors to detect and account for overflow that can occur in a multi-result vector that is passed in a chain of arithmetic units. Side band logic evaluates the LSBs in the operands for the reduced-precision operations to generate an expected value of performing the operation and compares the expected value to an actual value of the corresponding bits in the multi-result vector. If the expected and actual values match, then there was no overflow. However, if the values do not match, the side band logic updates the overflow value so that this overflow can be corrected once the final multi-result vector has been calculated.

An artificial neural network (ANN) system includes a processor, a virtual overflow detection circuit and a data format controller. The processor performs node operations with respect to a plurality of nodes included in each layer of an ANN to obtain a plurality of result values of the node operations and performs a quantization operation on the obtained plurality of result values based on a k-th fixed-point format for a current quantization of the each layer to obtain a plurality of quantization values. The virtual overflow detection circuit generates a virtual overflow information indicating a distribution of valid bit numbers of the obtained plurality of quantization values. The data format controller determines a (k+1)-th fixed-point format for a next quantization of the each layer based on the generated virtual overflow information. An overflow and/or an underflow are prevented efficiently by controlling the fixed-point format using the virtual overflow.

In various embodiments, a floating-point arithmetic circuit includes a range exception detection circuit and an output circuit. The range exception detection circuit may generate a selection signal that indicates whether a floating-point arithmetic result generated within the floating-point arithmetic circuit is within a specified range. The output circuit may output the floating-point arithmetic result in response to the selection signal indicating the floating-point arithmetic result is within a specified range. The output circuit may output a corresponding specified value in response to the selection signal indicating the floating-point arithmetic result is not within the specified range. Accordingly, floating-point arithmetic operations may be performed in combination with an operation that limits a range of an output to a specified range.

An arithmetic operation device causes a convolution arithmetic unit to perform a convolution arithmetic operation between a filter and target data corresponding to a size of the filter in each of a plurality of convolution layers constituting a neural network. The arithmetic operation device includes: a bit reduction unit that reduces a bit string corresponding to a first bit number from a least significant bit of the target data and reduces a bit string corresponding to a second bit number from a least significant bit of a weight that is an element of the filter for each convolution layer; and a bit addition unit that adds a bit string corresponding to a third bit number obtained by adding the first bit number and the second bit number to a least significant bit of a convolution arithmetic operation result output from the convolution arithmetic unit by inputting the target data and the weight after being reduced by the bit reduction unit to the convolution arithmetic unit.