A matrix calculation block for a graphical modeling environment that executes block diagrams. Blocks of the block diagram have input ports and/or output ports, and are connectable through the respective ports by signal lines for data transmission. The matrix calculation block includes: at least one input port configured to receive an input matrix signal; a calculation definition having at least one error condition check; at least one output port configured for emitting an output signal, the output signal being a vector signal or a matrix signal; and an error port configured for emitting an error signal. A value of the error signal indicates an error state of a plurality of predefined error states, which includes an error-free state. The value of the error signal depends on whether the at least one error condition check is fulfilled or not.

A neural processor and a control method of the neural processor are provided. The neural processor includes plurality of processing element groups, wherein each of the processing element groups includes a plurality of processing elements configured to perform a vector operation, an overflow accumulator configured to be engaged by a processing element in which an overflow or underflow occurs from among the plurality of processing elements, and a register configured to store information indicating the processing element as an owner processing element.

A processing device comprises a register configured to store a count value indicating a number of times overflow events have resulted from arithmetic operations performed by the processing device. An execution unit of the device, in response to performing an arithmetic operation having a result which extends beyond one of the predefined limit values for the floating-point format, stores a result value that is within the predefined limit values, and cause the count value to be incremented. The count value provides a performant way of determining the number of overflow events that have occurred during the arithmetic processing performed by the execution unit. The count value provides a metric that provides a measure of the inaccuracy imparted into the results of the application processing by overflow events.

A first input and a second input are added in hardware logic to determine an output value. receiving The first input comprises a first number of bits and the second input comprises a second number of bits, the second input being wider than the first input. The first input is added to the first number of least significant bits of the second input to determine a carry value. Using a third number of most significant bits of the second input, it is determined whether there is a risk of integer overflow, the third number being equal to the first number subtracted from the second number. The determined carry value and the determined risk of overflow are used to determine whether the addition of the first input and the second input will cause integer overflow. In response to determining that the addition will cause integer overflow, the output value is determined.

Multidimensional data mapped into one-dimensional data using a Z-ordering function is parsed to identify work packets to be processed. Dimensions of the multidimensional data and information identifying a valid region of the multidimensional data are obtained, where the valid region identifies work packets. At least part of a sequence within the one-dimensional data is determined, corresponding to positions within the multidimensional data lying in the valid region, by determining whether a position defined by a first value lies within the valid region. If the position does not lie within the valid region, an overflow value is calculated which causes a least significant bit that is a 1 in a binary representation of the first value to flip to a 0. The first value and the overflow value are summed to obtain a trial value which if lying within the valid region forms part of the sequence, wherein the sequence identifies work packets to be processed.