A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

A multiplication accumulating device and a method thereof are provided. The multiplication accumulating device includes a product generator, a plurality of registers, a product reducer, and an adder. The product generator performs a product operation on a multiplicand and a multiplier to generate a product result of 2N−1 columns. The product reducer is used to append data from a portion of the plurality of registers to the columns in the product result to generate an appending result of 2N−1 columns. The product reducer performs a reduction operation on the appending result according to a column height of each column in the appending result to obtain a reduced result. The product reducer renews the data in the plurality of registers according to the reduced result. The adder adds the data in the plurality of registers according to an accumulation signal to generate a multiplication accumulating operation result.

A multiplication accumulating device and a method thereof are provided. The multiplication accumulating device includes a product generator, a plurality of registers, a product reducer, and an adder. The product generator performs a product operation on a multiplicand and a multiplier to generate a product result of 2N−1 columns. The product reducer is used to append data from a portion of the plurality of registers to the columns in the product result to generate an appending result of 2N−1 columns. The product reducer performs a reduction operation on the appending result according to a column height of each column in the appending result to obtain a reduced result. The product reducer renews the data in the plurality of registers according to the reduced result. The adder adds the data in the plurality of registers according to an accumulation signal to generate a multiplication accumulating operation result.

Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.

The Non-Volatile Arithmetic Memory Operators (NV-AMO) consisting of non-volatile memory devices for storing non-volatile data are applied to perform the arithmetic operations over volatile variable data and the non-volatile data. The NV-AMO can save arithmetic computation power by reducing the data amount fetching from the memory units. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.

The Non-Volatile Arithmetic Memory Operators (NV-AMO) consisting of non-volatile memory devices for storing non-volatile data are applied to perform the arithmetic operations over volatile variable data and the non-volatile data. The NV-AMO can save arithmetic computation power by reducing the data amount fetching from the memory units. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.

A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.

A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.

Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.