Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

Neuron circuits are provided for spiking neural network apparatus having multiple such neuron circuits interconnected by links, each associated with a respective weight, for transmission of signals between neuron circuits. A neuron circuit includes a digital transmitter for generating trigger signals, indicating a state of the neuron circuit, on outgoing links of the circuit. The state is encoded in a time interval defined by these trigger signals. The neuron circuit includes a digital receiver for detecting such trigger signals on incoming links of the circuit, and digital accumulator logic. In response to detecting a trigger signal on an incoming link, the digital accumulator logic is adapted to generate a weighted signal dependent on the time interval and to accumulate the weighted signals generated from trigger signals on the incoming links to determine the state of the neuron circuit.

Neuron circuits are provided for spiking neural network apparatus having multiple such neuron circuits interconnected by links, each associated with a respective weight, for transmission of signals between neuron circuits. A neuron circuit includes a digital transmitter for generating trigger signals, indicating a state of the neuron circuit, on outgoing links of the circuit. The state is encoded in a time interval defined by these trigger signals. The neuron circuit includes a digital receiver for detecting such trigger signals on incoming links of the circuit, and digital accumulator logic. In response to detecting a trigger signal on an incoming link, the digital accumulator logic is adapted to generate a weighted signal dependent on the time interval and to accumulate the weighted signals generated from trigger signals on the incoming links to determine the state of the neuron circuit.

Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

A field programmable gate array (FPGA) has a 4-LUT (lookup table) that has four stages of multiplexers. The 4-LUT is fracturable. The 4-LUT being fracturable includes the capability to implement multiple LUTs in an instance of FPGA programming for functions from a group that includes adder functions and further functions. The 4-LUT has outputs exposed to programmable connection in accordance with FPGA programming. Outputs of the 4-LUT include an output of a first multiplexer in the third stage, an output of a multiplexer in the second stage, and an output of a multiplexer in the second or third stage of the 4-LUT.