A field programmable gate array (FPGA) has a 4-LUT (lookup table) that has four stages of multiplexers. The 4-LUT is fracturable. The 4-LUT being fracturable includes the capability to implement multiple LUTs in an instance of FPGA programming for functions from a group that includes adder functions and further functions. The 4-LUT has outputs exposed to programmable connection in accordance with FPGA programming. Outputs of the 4-LUT include an output of a first multiplexer in the third stage, an output of a multiplexer in the second stage, and an output of a multiplexer in the second or third stage of the 4-LUT.

An arithmetic circuit includes an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals based on the plurality of input signals; a first ripple carry adder (RCA) performing a first part of an accumulation operation on the first addition signals to generate a carry; a flip-flop; a second RCA performing a second part of the accumulation operation on the second addition signals and an output of the flop-flop; the first RCA latching the carry in the flip-flop after the accumulation operation is performed; and an output buffer latching an output signal of the first RCA and an output signal of the second RCA, and outputting a sum signal representing a sum of the plurality of input signals.

According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.

According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.

In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

An adder-subtractor circuit includes an inverting circuit configured to invert a first operand on a bit-by-bit basis to output a first inverted operand, a circuit having a function to perform a predetermined arithmetic operation and configured to output a second operand, a carry generating circuit configured to generate carries from the first inverted operand and the second operand, and an XOR circuit configured to perform a bit-by-bit XOR on the carries, the first operand, and the second operand.

An adder-subtractor circuit includes an inverting circuit configured to invert a first operand on a bit-by-bit basis to output a first inverted operand, a circuit having a function to perform a predetermined arithmetic operation and configured to output a second operand, a carry generating circuit configured to generate carries from the first inverted operand and the second operand, and an XOR circuit configured to perform a bit-by-bit XOR on the carries, the first operand, and the second operand.

A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.