The present disclosure relates to aft XIU-accumulating register, aft XIU-accumulating register circuit, and an electronic device. The XIU-accumulating register includes a first accumulating unit and a second accumulating unit. The first accumulating unit includes a first adder and a first register; the first adder is configured to accumulate fractional bit data of an accumulated variable, and the first register is configured to store an accumulated result of the fractional bit data and carry bit data of the accumulated result of the fractional bit data. The second accumulating unit includes a second adder and a second register; the second adder is configured to accumulate integer bit data of the accumulated variable, and the second register is configured to store an accumulated result of the integer bit data.

The present disclosure relates to aft XIU-accumulating register, aft XIU-accumulating register circuit, and an electronic device. The XIU-accumulating register includes a first accumulating unit and a second accumulating unit. The first accumulating unit includes a first adder and a first register; the first adder is configured to accumulate fractional bit data of an accumulated variable, and the first register is configured to store an accumulated result of the fractional bit data and carry bit data of the accumulated result of the fractional bit data. The second accumulating unit includes a second adder and a second register; the second adder is configured to accumulate integer bit data of the accumulated variable, and the second register is configured to store an accumulated result of the integer bit data.

A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.

A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.

An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

The present disclosure relates generally to techniques for enhancing packing density of carry-chains implemented on an integrated circuit. In particular, a packed-carry chain may be implemented to redistribute and/or emulate the logic of a first number of arithmetic logic cells of a first and/or second carry-chain using a second number of arithmetic logic cells less than or equal to the first number. By fitting the first and second carry-chain into such a packed carry-chain, the area consumed to perform the arithmetic operations of the first and second carry-chain may be reduced. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., wiring, area, and power).

The present disclosure relates generally to techniques for enhancing packing density of carry-chains implemented on an integrated circuit. In particular, a packed-carry chain may be implemented to redistribute and/or emulate the logic of a first number of arithmetic logic cells of a first and/or second carry-chain using a second number of arithmetic logic cells less than or equal to the first number. By fitting the first and second carry-chain into such a packed carry-chain, the area consumed to perform the arithmetic operations of the first and second carry-chain may be reduced. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., wiring, area, and power).

A logic circuit comprising: inputs for receiving multiple n-bit numbers, n being greater than one; and an adder capable of receiving m n-bit numbers, m being greater than one, and forming an output representing the sum of those numbers, the adder having a plurality of single-bit stages and being configured to form the sum by subjecting successive bits of each of the numbers to an operation in a respective one of the single-bit stages, the single-bit stages being such that the adder has insufficient capacity to add all possible combinations of bits in a respective bit position of m n-bit numbers; the addition circuit being configured to add the multiple n-bit numbers by: in the adder, adding a first one of the n-bit numbers to a value corresponding to a set of non-consecutive bits of another of the n-bit numbers to form a first intermediate value; adding the first intermediate value to a value corresponding to the bits of the said other of the n-bit numbers other than those in the said set to form a sum; and outputting the sum.

An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

This disclosure relates to an adder circuit. The adder circuit comprises an operand input and a second operand input to an XNOR cell. The XNOR cell may be configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell may transform the output of the XNOR cell into a carry out signal.