A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths (e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/O) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multiplier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations from a general-purpose processor.

One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One advantage of the disclosed embodiments is that, by using a common fused floating point multiply-add unit to perform arithmetic operations on integers of arbitrary width, the method avoids the area and power penalty of having additional dedicated integer units.

One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One advantage of the disclosed embodiments is that, by using a common fused floating point multiply-add unit to perform arithmetic operations on integers of arbitrary width, the method avoids the area and power penalty of having additional dedicated integer units.

An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Arithmetic circuitry according one embodiment performs a first arithmetic operation by AND operations and XOR operations. The first arithmetic operation corresponds to p multiplications (p is an integer of 2 or more) to be performed in series. The p multiplications are respectively represented by p order-3 tensors each receiving two elements of a Galois field as inputs and outputting one element as a result of multiplication of the two elements. The AND operations calculate AND values of a plurality of elements used in the p multiplications. The XOR operations are based on a contracted tensor obtained by contraction of an order-3p tensor obtained by a direct product of the p order-3 tensors and the AND values.

Arithmetic circuitry according one embodiment performs a first arithmetic operation by AND operations and XOR operations. The first arithmetic operation corresponds to p multiplications (p is an integer of 2 or more) to be performed in series. The p multiplications are respectively represented by p order-3 tensors each receiving two elements of a Galois field as inputs and outputting one element as a result of multiplication of the two elements. The AND operations calculate AND values of a plurality of elements used in the p multiplications. The XOR operations are based on a contracted tensor obtained by contraction of an order-3p tensor obtained by a direct product of the p order-3 tensors and the AND values.