G06F9/264

CONTROL OF INSTRUCTION ISSUE BASED ON ISSUE GROUPS

Issue group allocation circuitry controls allocation of each micro-operation to one of a plurality of issue groups, depending on detection of register conflicts between micro-operations, the register conflicts concerning access to registers of a first register set. A given micro-operation is allocated to a selected issue group for which no micro-operation already allocated to the selected issue group has a register conflict with the given micro-operation and the selected issue group is a younger issue group than any issue group already allocated an older micro-operation than the given micro-operation for which a register conflict is detected between the given micro-operation and the older micro-operation. Issue circuitry controls issue of the micro-operations based on the issue groups, to prevent any instruction in a given issue group being issued until all micro-operations in any older issue group than the given issue group have been issued.

Computing chip and instruction processing method to access source operands in private registers using a relative distance index

Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.