Systems and methods for operating a processor include determining confidence levels, such as high, low, and medium confidence levels, associated with in-flight branch instructions in an instruction pipeline of the processor, based on counters used for predicting directions of the in-flight branch instructions. Numbers of in-flight branch instructions associated with each of confidence levels are determined. A weighted sum of the numbers weighted with weights corresponding to the confidence levels is calculated and the weighted sum is compared with a threshold. A throttling signal may be asserted to indicate that instructions are to be throttled in a pipeline stage of the instruction pipeline based on the comparison.

Synchronization points are inserted into a program code to be monitored, and are associated with different branches resulting from execution of an indirect branch instruction. The synchronization points can be accessed by the monitored program code for the purpose of identifying which branch to use during execution of the indirect branch instruction of the monitored program code.

Branch prediction in a computer processor, includes: fetching an instruction, the instruction comprising an address, the address comprising a first portion of a global history vector and a global history vector pointer; performing a first branch prediction in dependence upon the first portion of the global history vector; retrieving, in dependence upon the global history vector pointer, from a rolling global history vector buffer, a second portion of the global history vector; and performing a second branch prediction in dependence upon a combination of the first portion and second portion of the global history vector.

A method of broadcasting event messages in a system-on-chip having system circuitry and monitoring circuitry for monitoring the system circuitry, the monitoring circuitry comprising units connected in a tree-based structure for routing communications through the system-on-chip, the tree-based structure comprising branches extending from a root unit, each branch comprising a plurality of units, each unit connected to a single unit above in the branch and a single unit below in the branch, whereby each unit routes communications to and from individually addressable entities above that unit in its branch, the tree-based structure further comprising crosslinks connecting corresponding units of adjacent branches, the method comprising: if an event is generated at an event unit or its local subsystem, routing an event message directly from that event unit to: any adjacent unit above the event unit in the event unit's branch, any adjacent unit below the event unit in the event unit's branch, and any corresponding unit of an adjacent branch to which the event unit is connected via a crosslink.

Embodiments are provided for mitigation of branch misprediction penalty in hardware multi-thread microprocessors. In some embodiments, a hardware multi-thread microprocessor includes first stage circuitry that fetches a pair of consecutive instructions of a program executed in a thread. Such microprocessor also includes second stage circuitry that determines, during a clock cycle, that a first instruction in that pair is a branch instruction. The first stage circuitry fetches, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction. Such microprocessor further includes third stage circuitry that determines that the branch prediction is a misprediction during the second clock cycle. The first stage circuitry sends the second instruction to the second stage circuitry during a third clock cycle after the second clock cycle. The second stage circuitry decodes the second instruction during the third clock cycle.

A method for computing in a thread-based environment provides manipulating an execution mask to enable and disable threads when executing multiple conditional function clauses for process instructions. Execution lanes are controlled based on execution participation for the process instructions for reducing resource consumption. Execution of particular one or more schedulable structures that include multiple process instructions are skipped based on the execution mask and activating instructions.

Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

A method for trace prediction includes using trace prediction to predict a trace specifying branch decisions. When a branch misprediction is detected, trace prediction is terminated and prediction is continued using branch prediction.

A method for a delayed branch implementation by using a front end track table. The method includes receiving an incoming instruction sequence using a global front end, wherein the instruction sequence includes at least one branch, creating a delayed branch in response to receiving the one branch, and using a front end track table to track both the delayed branch the one branch.

Embodiments provide techniques for estimating seasonal indices for multiple periods. Some embodiments can receive a signal comprising a plurality of measures sampled over a span of time from an environment in which one or more processes are being executed. Some embodiments may then extract a seasonal effector and a de-seasonalized component from the signal. Next, some embodiments can apply one or more spline functions to the seasonal effector to generate a first model. Some embodiments may then apply a linear regression technique to the de-seasonalized component to generate a second model. Some embodiments may then initiate actions associated with the code. Some embodiments may then generate a forecast of the signal based on the first model and the second model. Next, some embodiments may initiate, based at least in part on the forecast, one or more actions associated with the environment.