There is provided an apparatus including input circuitry that receives input data. Output circuitry outputs a sequence of instructions to be executed by data processing circuitry, at least some of the instructions being grouped into functions and generation circuitry performs a generation process to generate the sequence of instructions using the input data. The generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation performed during execution of the sequence of instructions and the stored state of control flow speculation is maintained between the functions.

Methods and apparatuses relating to instruction set architecture (ISA) based and automatic load tracking hardware for opportunistic re-steer of data-dependent flaky branches are described. In one embodiment, a processor includes a pipeline circuit comprising a decoder to decode instructions into decoded instructions and an execution circuit to execute the decoded instructions, a branch predictor circuit to generate a predicted path for a branch instruction, and a branch re-steer circuit to, for the branch instruction dependent on a result from a load instruction, check if an instruction received by the pipeline circuit is the load instruction, and when the instruction received by the pipeline circuit is the load instruction, check for a write back of the result from the load instruction between a decode of the branch instruction with the decoder and an execution of the branch instruction with the execution circuit, and when the predicted path differs from a path based on the result from the load instruction, re-steer the branch instruction in the pipeline circuit to the path and cause execution of the branch instruction for the path based on the result from the load instruction.

Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.

In an embodiment, an indirect branch predictor generates indirect branch predictions for indirect branch instructions. For relatively static branch instructions, the indirect branch predictor may be configured to use a PC corresponding to the indirect branch instruction to generate a target prediction. The indirect branch predictor may be configured to identify at least one dynamic indirect branch instruction and may use a different PC than the PC corresponding to the indirect branch instruction to generate the target prediction (e.g. the most recent previous PC associated with a taken branch (“the previous taken PC”). For some dynamic indirect branch instructions, the previous taken PC may disambiguate different target addresses (e.g. there may be a correlation between the previous taken PC and the target address of the indirect branch instruction).

Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.

Systems and methods for managing optimized branching in executable instructions are disclosed. In one implementation, a processing device may identify, in a sequence of executable instructions, a branching instruction associated with a safe static key, the branching instruction specifying a first target location. The processing device may determine whether a value of the safe static key is initialized. Responsive to determining that the value of the safe static key is initialized, the processing device may further replace the branching instruction with an unconditional branching instruction specifying the first target location. Responsive to determining that the value of the safe static key is uninitialized, the processing device may replace the branching instruction with a conditional branching instruction specifying the first target location.

There is provided an apparatus that includes input circuitry to receive input data and output circuitry to output a sequence of instructions to be executed by data processing circuitry. Generation circuitry performs a generation process to generate the sequence of instructions using the input data. The sequence of instructions comprises an indirect control flow instruction having a field that indicates where a target of the indirect control flow instruction is stored. The generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation after execution of the indirect control flow instruction. The at least one of the instructions in the sequence of instructions that stores the state of control flow speculation is inhibited from being subject to data value speculation by the data processing circuitry.

Embodiments described herein provide for a computing device comprising a hardware processor including a processor trace module to generate trace data indicative of an order of instructions executed by the processor, wherein the processor trace module is configurable to selectively output a processor trace packet associated with execution of a selected non-deterministic control flow transfer instruction.

Systems and methods for managing optimized branching in executable instructions are disclosed. In one implementation, a processing device may identify, in a sequence of executable instructions, a jump instruction associated with a safe static key. Responsive to determining that a condition is satisfied, the processing device may further replace the jump instruction with an optimized transfer of control instruction provided by one of: a no operation instruction or an unconditional jump instruction specifying a first jump target location. Responsive to determining that a rate of modification of the safe static key exceeds a threshold rate, the processing device may also replace the optimized transfer of control instruction with a conditional jump instruction specifying the first jump target location.

A computer system includes a first predictor circuit configured to generate a first predictor signal, and a second predictor circuit configured to generate a second predictor signal different from the first predictor signal. The computer system further includes a TIP arbiter configured to receive the first predictor signal and the second predictor signal, and to select one of the first predictor signal or the second predictor signal as a final prediction of a target address for a fetched branch instruction. The selection is based at least in part on a comparison between a branch address of the fetched branch instruction and a stored tag value, along with a counter value stored in the arbiter entry.