An example embodiment combines use of a branch predictor with cache-like storage of previously executed branch targets to improve processor performance while minimizing hardware cost. The branch predictor is configured to predict both conditional branch and indirect branch targets and includes a combined predictor table configured to store at least one tagged conditional branch prediction in combination with at least one tagged indirect branch target prediction. The at least one tagged indirect branch target prediction is configured to include a predicted partial target address of a complete target address, the complete target address associated with an indirect branch instruction of a processor. The predictor includes prediction logic configured to use the predicted partial target address to produce a predicted complete target address of the complete target address for use by the processor prior to execution of the indirect branch instruction.

A processor-implemented method is provided. The processor-implemented includes reading, by a processor, an instruction stream by fetching instructions from an instruction cache of the processor. The processor then executes a branch prediction operation based on a context of the instruction stream and an index when one of the instructions includes a branch instruction. The branch prediction operation output a prediction and a context. The processor then compares the context of the instruction stream and the context from the branch prediction operation to determine whether to execute a stop fetch.

A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

In one embodiment, a processor comprises a decoder to decode a first instruction, the first instruction comprising an opcode and at least one parameter, the opcode to identify the first instruction as an instruction associated with an indirect branch, the at least one parameter indicative of whether the indirect branch is allowed; and circuitry to generate an error message based on the at least one parameter.

The present disclosure includes a mispredict recovery apparatus, which may comprise an instruction execution unit, a branch predictor, and a misprediction recovery unit (MRU). The MRU may provide discrete cycle predictions after a misprediction redirect from the instruction execution unit. The MRU may include a branch confidence filter to generate prediction confidence information for predicted branches. The MRU may include a tag content-addressable memory (CAM). The tag CAM may store frequently mispredicting low-confidence branches, probe the misprediction redirect, and obtain the prediction confidence information from the branch confidence filter. The MRU may include a mispredict recovery buffer (MRB) to store an alternate path for frequently mispredicting low-confidence branches present in the tag CAM without storing the instructions themselves. Also disclosed is a method for recovering from mispredicts associated with the instruction fetch pipeline.

A method and apparatus are provided. The method includes executing a plurality of threads in a temporal dimension, executing a plurality of threads in a spatial dimension, determining a branch target address for each of the plurality of threads in the temporal dimension and the plurality of threads in the spatial dimension, and comparing each of the branch target addresses to determine a minimum branch target address, wherein the minimum branch target address is a minimum value among branch target addresses of each of the plurality of threads.

A computer system includes a first predictor circuit configured to generate a first predictor signal, and a second predictor circuit configured to generate a second predictor signal different from the first predictor signal. The computer system further includes a TIP arbiter configured to receive the first predictor signal and the second predictor signal, and to select one of the first predictor signal or the second predictor signal as a final prediction of a target address for a fetched branch instruction. The selection is based at least in part on a comparison between a branch address of the fetched branch instruction and a stored tag value, along with a counter value stored in the arbiter entry.

Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.

Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.

A method, computer program product and/or system is disclosed. According to an aspect of this invention, one or more processors receive an indirect jump instruction comprising a target address offset and a maximal offset value. One or more processors determine whether the target address offset is valid by comparison of the target address offset and the maximal offset value and one or more processors execute a jump operation based on whether the target address offset is valid. In some embodiments of the present invention, the jump operation comprises one or more processors executing an instruction located at a target address referenced by the target address offset if the target address offset is valid. In some embodiments, the jump operation further comprises one or more processors raising an exception if the target address offset is not valid.