An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

Systems and methods for illumination power, management and control can include lighting fixtures, lighting controllers, databases, and gateways. The lighting controllers can power the lighting fixtures, control the lighting fixtures, and store fixture state data and controller state data. The lighting controllers can be connected to building mains power (e.g., 240 VAC) and provide DC power to the lighting fixtures. The lighting controllers can read state data from and control the fixtures via a digital interface. The Database server can store user profiles, site profiles, fixture property data, and controller property data. The gateway can read and modify the state data stored by the lighting controllers, and can query the database server for the property data. The gateway can also provide a user interface through which users, based on authorization, can read and write the state data (e.g., fixture on/off) and the property data.

A method and apparatus for implementing power modes in microcontrollers (MCUs) using power profiles. In one embodiment of the method, a central processing unit (CPU) of the MCU executes a first instruction for calling a subroutine stored in a memory of the MCU, wherein the first instruction comprises a first parameter to be passed to the subroutine. Thereafter the CPU writes a first value to a first special function register (SFR) of the MCU in response to executing the first instruction, wherein the first value is related to the first parameter. The MCU operates in a first power mode in response to the CPU writing the first value to the first SFR. The CPU also executes a second instruction for calling the subroutine, wherein the second instruction comprises a second parameter to be passed to the subroutine. In response the CPU writes a second value to a second SFR of the MCU in response to executing the second instruction, wherein the second value is related to the second parameter. The MCU operates in a second power mode in response to the CPU writing the second value to the second SFR. The MCU consumes more power operating in the first power mode than it does when operating in the second power mode.

The present disclosure provides a data screening device and method, which employ a storage unit and a register unit, and are capable of performing operations on data of different storage structures and different sizes efficiently.

A computer implemented method includes detecting a current context of a user device, comparing the current context of the user device to various power schemes associated with various saved contexts, selecting a first power scheme having a saved context commensurate with the current context, and saving the first power scheme as a current power scheme of the user device.

A system and method of minimizing the context saved when the processing unit is disclosed. The kernel attempts to save time and memory by reducing or eliminating the amount of context that is saved or restored in certain situations. Specifically, if there is no currently executing, the kernel does not save any context before switching to another task. Similarly, if there is no new task to execute, the kernel does not restore any context before making the context switch. Rather, the kernel applies a lightweight context. In some embodiments, the idle context uses the ISR stack rather than having a dedicated stack. This system and method reduces the time required for certain context switches and also saves memory.

A system and method for utilizing the processing power of computing devices such as smart devices are provided. The system includes one or more distributed smart devices and a management server that communicates with the smart devices in order to determine whether they are idle and whether viable compute tasks are present that can be performed on the smart devices based on the smart device's status, configuration, utility and network parameters, and availability. Some tasks may be performed in low power mode to save energy.

A system and method for utilizing the processing power of computing devices such as smart devices are provided. The system includes one or more distributed smart devices and a management server that communicates with the smart devices in order to determine whether they are idle and whether viable compute tasks are present that can be performed on the smart devices based on the smart device's status, configuration, utility and network parameters, and availability. Some tasks may be performed in low power mode to save energy.

The present disclosure provides an operation device, comprising: an operation module for executing a neural network operation; and a power conversion module connected to the operation module, for converting input neuron data and/or output neuron data of the neural network operation into power neuron data. The present disclosure further provides an operation method. The operation device and method according to the present disclosure reduce the cost of storage resources and computing resources and increase the operation speed.

A method of controlling an operation of a multi-core system including a plurality of processor cores, includes, monitoring task execution delay times with respect to tasks respectively assigned to the plurality of processor cores, monitoring core execution delay times with respect to the plurality of processor cores and controlling an operation of the multi-core system based on the task execution delay times and the core execution delay times.