A system and apparatus comprise at least one power supply connected to a terminal bloc, an I/O system configured to receive instructions provided to the control system, a control block connected to the I/O system wherein the instructions provided to the I/O system are converted to a serial output; and a puck connected to the serial output and configured to receive power from the terminal block, to process the serial output, and to output a current.

A method for synchronizing startup of a plurality of power supplies in an electrical system includes supplying input power to a first power supply to supply power to an auxiliary converter and an auxiliary controller. The method also includes monitoring, via the auxiliary controller, a signal shared by each of the plurality of power supplies. The method further includes incrementally increasing, via the auxiliary controller, a value of the shared signal to a next incremental value of a plurality of specified values. The method also includes enabling, via the auxiliary controller, each of the power supplies to supply power to a load when the value of the shared signal is set to a maximum value of the specified values.

Disclosed embodiments relate to systems and methods to skip inconsequential matrix operations. In one example, a processor includes decode circuitry to decode an instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode indicating that the processor is to multiply each element at row M and column K of the first source matrix with a corresponding element at row K and column N of the second source matrix, and accumulate a resulting product with previous contents of a corresponding element at row M and column N of the destination matrix, the processor to skip multiplications that, based on detected values of corresponding multiplicands, would generate inconsequential results, scheduling circuitry to schedule execution of the instruction; and execution circuitry to execute the instructions as per the opcode.

A system and apparatus comprise at least one power supply connected to a terminal bloc, an I/O system configured to receive instructions provided to the control system, a control block connected to the I/O system wherein the instructions provided to the I/O system are converted to a serial output; and a puck connected to the serial output and configured to receive power from the terminal block, to process the serial output, and to output a current.

In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.

Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

A method of identifying an unsupported storage device on a server is disclosed as including providing the server with a baseboard management controller (BMC), the BMC obtaining vital product data (VPD) from a storage device on the server, the BMC comparing the VPD from the storage device with one or more approved VPDs, and the BMC issuing an output in response to said comparison.

A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.