In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.

Systems, methods, and software can be used to analyze security risks of a binary software code. In some aspects, a computer-implemented method comprises: receiving, by at least one hardware processor, a binary software code; determining, by the at least one hardware processor, that the binary software code accesses one or more network addresses; for each of the one or more network addresses that are accessed by the binary software code: determining, by the at least one hardware processor, whether the binary software code uses an insecure network protocol to access the network address; and generating, by the at least one hardware processor, a security notification indicating the network address that is accessed by the binary software code using the insecure network protocol.

A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.

An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

An apparatus has floating-point multiplying circuitry to perform a floating-point multiply operation to multiply first and second floating-point operands to generate a product floating-point value. Shared hardware circuitry of the floating-point multiplying circuitry is reused to also support a floating-point scaling instruction specifying an input floating-point operand and an integer operand, which causes a floating-point scaling operation to be performed to generate an output floating-point value corresponding to a product of the input floating-point operand and a scaling factor 2.sup.X, where X is an integer represented by the integer operand.

This disclosure relates to methods and mechanisms for matrix computing which include machine embodiments with one or more matrix storage spaces for holding matrices and arrays for computing, where a matrix or an array is accessible by its columns, by its rows, or both, individually, or concurrently. A set of methods and mechanisms to build a large capacity instruction set with multi-length instructions to load, store, and compute with these matrices and arrays are also disclosed. Methods and access control mechanisms with keys to secure, share, lock and unlock regions in the storage space for matrices and arrays under the control of an operating system or a virtual machine hypervisor by permitted threads and processes are also disclosed. Methods and mechanisms to handle long immediate operands for use by shorter instructions using a payload instruction are also disclosed. The structure of the instructions with key instruction fields and a method for determining instruction length are also disclosed.

A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.

An arithmetic processing device includes: a decoder configured to write an immediate value to a register in a case where an instruction to be executed is an instruction not involving data reading from the register; and a processor configured to read data from the register and write a computing result based on the read data to the register in a case where an instruction to be executed by the decoder is an instruction involving data reading from the register.