An apparatus and method are described for performing split lock operations in a multi-core processor. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution; a shared cache to be shared by two or more of the plurality of cores; a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting at least two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state; at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated; the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine.

Trace circuitry 22, 6 forms trace objects 34 representing a sequence of executed program instructions and comprising a start address indicator indicating a start address of a sequence of executed program instructions, a branch outcome indicator indicating a sequence of branch outcomes within the sequence of executed program instructions starting from the start address and a count indicator indicating a count of times the sequence of branch outcomes was detected. The trace circuitry may be on-chip 22 or off-chip 6. A trace object may include an indicator of a start address of a next sequence of program instructions to be followed following the sequence of program instructions represented by the trace object concerned.

Executing system call vectored (SCV) instructions in a multi-slice processor including receiving, by an instruction fetch unit, a SCV instruction, wherein the SCV instruction is a system call from an operating system; sending the SCV instruction to a branch issue queue; determining, by the branch issue queue, that the SCV instruction is next-to-complete; issuing the SCV instruction to a branch resolution unit; and executing the SCV instruction by the branch resolution unit.

A processor has an execution pipeline that executes microinstructions and an instruction translator that translates architectural instructions into the microinstructions. The instruction translator has a memory that holds microcode instructions and provides a fetch quantum of a plurality of microcode instructions per clock cycle, a queue that holds microcode instructions provided by the memory, and a branch decoder that decodes the fetch quantum to detect local branch instructions, causes microcode instructions of the fetch quantum up to but not including a first-in-program-order local branch instruction to be written to the queue, and prevents the first-in-program-order local branch instruction and following microcode instructions of the fetch quantum from being written to the queue. Local branch instructions are resolved by the instruction translator rather than the execution pipeline. Microcode translators translate multiple microcode instructions received from the queue per clock cycle into microinstructions for provision to the execution pipeline.

One embodiment provides an accelerator circuitry. The accelerator circuitry includes accelerator processor circuitry; accelerator memory circuitry; processor trace (PT) decoder circuitry and control flow integrity (CFI) checker circuitry. The PT decoder circuitry is to at least one of receive and/or retrieve PT data from a host device. The PT decoder circuitry is further to extract a target instruction pointer (TIP) packet from the PT data and to decode the TIP packet to yield a runtime target address. The CFI checker circuitry is to determine, at runtime, whether a control flow transfer of an indirect branch instruction to the runtime target address corresponds to a control flow violation based, at least in part, on control flow (CF) information (info) stored to an accelerator CF info store.

An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.

An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.

This invention provides a cache system and method based on instruction read buffer (IRB). When applied to the field of processor, it is capable of filling instructions to the instruction read buffer which can be directly accessed by processor core and the processor core outputs instruction to the processor core for execution autonomously and achieve a high cache hit rate.

The present invention provides a multi-issue processor system and method. When applied to processors, it is capable of achieving a high cache hit rate by filling the instruction to the cache which the processor core can directly access before the execution of an instruction. According to the technical solutions of this invention, for multi-issue processor systems which need instruction translation, it can improve the performance of the processor by avoiding repeated address translation.

Various embodiments are generally directed to an apparatus, method and other techniques to determine whether a target address of a register for an execution instruction is valid or invalid based on a comparison between the target address and one or more valid target addresses stored in a storage, increase a number of invalid target addresses if the target address is invalid, and determine whether the number of invalid target addresses is greater than an invalid target address threshold. Various embodiments may also include initiating a security measure to prevent a security breach if the number of invalid target addresses is greater than the invalid target address threshold or executing the execution instruction if the number of invalid target addresses is less than or equal to the invalid target address threshold.