Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

A processor includes: a storage unit that stores instructions; a counting unit that specifies an instruction to be decoded by a count value; a decoding unit that decodes an instruction; and a control unit that, when the decoded instruction is a repeat instruction, updates the count value of the counting unit so as to cause repeat target instructions in number corresponding to a designated number of instructions, out of instructions succeeding the repeat instruction, to be repeatedly executed a designated number of repetition times, and generates updated operands being operation objects of the repeat target instructions that are to be executed for the second or later time, and when the repeat target instructions are to be executed for the second or later time, updates operands of the repeat target instructions for use in the second or later time execution, to the generated updated operands and outputs the updated operands.

Optimization of captured loops in a processor for optimizing loop replay performance, and related methods and computer-readable media are disclosed. The processor includes a loop buffer circuit configured to detect loops. In response to a detected loop, the loop buffer circuit is configured to capture loop instructions in the detected loop and replay the captured loop instructions in the instruction pipeline to be processed and executed for subsequent iterations of the loop. The loop buffer circuit is configured to determine if loop optimizations are available to be made based on a captured loop to enhance performance of loop replay. If the loop buffer circuit determines loop optimizations are available to be made based on a captured loop, the loop buffer circuit is configured to perform such loop optimizations so that such loop optimizations can be realized when the captured loop is replayed to enhance replay performance of the captured loop.

A system includes a hardware compare and swap (CAS) module communicatively coupled to a bus, the CAS module to perform an atomic operation in response to a first request from a first request agent for the atomic operation to be performed on a data value that is shared among a plurality of request agents and obtain a first result value. The atomic operation includes initiating a CAS command via the bus. The CAS module performs the atomic operation in response to a second request from a second request agent and obtains a second result value. Responsive to determining a failure to successfully process one or more of the first request or the second request, the hardware CAS module repetitively performs the atomic operation, for one or more of the first request or the second request.

The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

A decoding logic method is arranged to execute a zero-overhead loop in an embedded digital signal processor (DSP). In the method, instruction data is fetched from a memory, and a plurality of instruction tokens, which are derived from the instruction data, are stored in a token buffer. A first portion of one or more instruction tokens from the token buffer are passed to a first decode module, which may be an instruction decode module, and a second portion of the one or more instruction tokens from the token buffer are passed to a second decode module, which may be a loop decode module. The second decode module detects a special loop instruction token, and based on the detection of the special loop instruction token, a loop counter is conditionally tested. Using the first decode module, at least one instruction token of an iterative algorithm is assembled into a single instruction, which is executable in a single execution cycle. Based on the conditional test of the loop counter, the first decode module further assembles a loop branch instruction of the iterative algorithm into the single instruction executable in one execution cycle.

In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.