Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction.

An information processing apparatus includes: a memory; and a processor configured to: acquire an instruction sequence including plural instructions; generate plural candidates of new instruction sequences capable of obtaining an execution result as same as in the instruction sequence, by replacing at least a part of plural nop instructions included in the instruction sequence with a wait instruction that waits for completion of all preceding instructions; delete any one of the nop instructions and the wait instruction from each of the new instruction sequences, when the execution result does not change in case any one of the nop instructions and the wait instruction is deleted from the new instruction sequences in the candidates; and select a one candidate among the candidates subjected to the delete, the one candidate including the number of instructions equal to or less than a certain number, and having a smallest number of execution cycles.

A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable/restricting actions associated with the program instruction. A related memory component and related methods are also disclosed.

A method for implementing a function jump includes receiving a first function, searching, for an address of the first function, a first data structure in which addresses of a plurality of functions are stored, where a patch function used to replace the first function is available when the address of the first function is found, searching a second data structure for an address of the patch function based on the address of the first function, where correspondences between a plurality of functions and patch functions of the functions are stored in the second data structure, jumping from the first function to the patch function of the first function based on the address of the patch function of the first function, and executing the patch function of the first function to respond to the call to the first function.

A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable/restricting actions associated with the program instruction. A related memory component and related methods are also disclosed.

A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable/restricting actions associated with the program instruction. A related memory component and related methods are also disclosed.

A method for implementing a function jump includes receiving a first function, searching, for an address of the first function, a first data structure in which addresses of a plurality of functions are stored, where a patch function used to replace the first function is available when the address of the first function is found, searching a second data structure for an address of the patch function based on the address of the first function, where correspondences between a plurality of functions and patch functions of the functions are stored in the second data structure, jumping from the first function to the patch function of the first function based on the address of the patch function of the first function, and executing the patch function of the first function to respond to the call to the first function.

Methods, systems and computer program products are provided for automated runtime configuration for dataflows to automatically select or adapt a runtime environment or resources to a dataflow plan prior to execution. Metadata generated for dataflows indicates dataflow information, such as numbers and types of sources, sinks and operations, and the amount of data being consumed, processed and written. Weighted dataflow plans are created from unweighted dataflow plans based on metadata. Weights that indicate operation complexity or resource consumption are generated for data operations. A runtime environment or resources to execute a dataflow plan is/are selected based on the weighted dataflow and/or a maximum flow. Preferences may be provided to influence weighting and runtime selections.

In one embodiment, an apparatus includes: a control circuit to enable a comparison circuit based on a dynamic update to a hook table and a patch table; and the comparison circuit coupled to the control circuit to compare an address of a program counter to at least one address stored in the hook table, and in response to a match between the address of the program counter and the at least one address stored in the hook table, cause a jump from code stored in a read only memory to patch code stored in a patch storage. Other embodiments are described and claimed.

A method, computer program product, and system identify a low-cost time to re-boot a system. The method includes a processor obtaining a request for a re-boot of a system. The processor obtains identifiers of uncompleted tasks executing in the system. Based on obtaining the identifiers, the processor obtains a task cost of each task of the uncompleted tasks, where a value of the task cost of each task relates to a portion of each task completed by the processor at a given time. The processor determines, based on the task costs associated with the uncompleted tasks, a re-boot cost for re-booting the system at the given time. The processor determined a system cost for not re-booting the system at the given time. The processor compares the re-boot cost to the system cost to determine whether to re-boot the system at the given time in response to the request.