A method for runtime self-protection of an application program includes, before running the application program, identifying input and output points in runtime code (24) of the program. The input points are instrumented so as to cause the program to sense and cache potentially malicious inputs to the program. The output points are instrumented so as to cause the program to detect outputs from the program corresponding to the cached inputs. While running the application program, upon detecting, at an instrumented output point, an output corresponding to a cached input, a vulnerability of a target of the output to the cached input is evaluated. A protective action is invoked upon determining that the output is potentially vulnerable to the cached input.

Modification of the execution of a platform-independent first method of an application within an integrated circuit card having a first non-volatile memory, a second rewritable non-volatile memory, a virtual machine and a processor unit, wherein said platform-independent first method includes a first operations sequence and a second operations sequence. Checking if there is a call within said platform-independent first method to a specific second method, having one parameter; if there is such a call and if said specific second method is not platform-independent, checking if there is an alternate function associated to said platform-independent first method stored in a memory of said integrated circuit card; if there is an associated alternate function: executing said alternate function to replace said first operations sequence; executing the second operations sequence of said platform-independent first method; otherwise executing by the first operations sequence and the second operations sequence of said platform-independent first method.

An information processing apparatus includes: a memory configured to store a first code; and a processor configured to compile a source file to generate the first code, wherein the processor: generates a second code, which is executable by the processor, based on a result of analysis of the source program; and divides the second code into blocks of a size equal to or smaller than a given size including a reservation region to generate the first code.

A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.

An information processing system includes a memory and processors. The memory stores flow information and flow identification information for each sequence of processes performed by using electronic data. The flow information defines program identification information identifying programs for executing the sequence of processes, and an execution order of the programs. The processors execute computer-executable instructions stored in the memory to execute a process including receiving information relating to the electronic data and flow identification information, from a device coupled to the information processing system; acquiring the flow information stored in association with the received flow identification information; provisionally executing the sequence of processes based on the received information and the acquired flow information; and executing the sequence of processes based on the received information and the acquired flow information, upon determining that an error has not occurred in the provisional execution of the sequence of processes.

An application located in one or more first memory regions is executed. The application has a separate modified portion, which is located in one or more second memory regions. A request is obtained to access one of a first memory region or a second memory region, the request including an address of a first type. Based on obtaining the request, the address is translated to another address. The other address is of a second type and indicates the first memory region or the second memory region. The translating is based on an attribute associated with the address, in which the attribute is used to select information from a plurality of information concurrently available for selection. The plurality of information provide multiple addresses of the second type, one of which is the other address. The other address is used to access the first memory region or the second memory region.

The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to implement a patch routine to change the behavior of at least a portion of the integrated circuit. In this manner, the original design of the integrated circuit may be altered.

A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching is provided for just a small area of the possible flash memory map, and program flow is controlled by presenting the CPU core's own address to redirect the program counter to the patch area.

An apparatus and method for updating a shader program based on a current state. For example, one embodiment of a method comprises: identifying a first plurality of instructions which are dependent on a non-orthogonal state (NOS); marking the each of the first plurality of instructions which are dependent on the NOS; detecting a current NOS; and dynamically patching the marked instructions for the current NOS.

A method, computer program product, and system identify a low-cost time to re-boot a system. The method includes a processor obtaining a request for a re-boot of a system. The processor obtains identifiers of uncompleted tasks executing in the system. Based on obtaining the identifiers, the processor obtains a task cost of each task of the uncompleted tasks, where a value of the task cost of each task relates to a portion of each task completed by the processor at a given time. The processor determines, based on the task costs associated with the uncompleted tasks, a re-boot cost for re-booting the system at the given time. The processor determined a system cost for not re-booting the system at the given time. The processor compares the re-boot cost to the system cost to determine whether to re-boot the system at the given time in response to the request.