An integrated circuit such as, for example a graphics processing unit (GPU), includes a dynamic power controller for adjusting operating voltage and/or frequency. The controller may receive current power used by the integrated circuit and a predicted power determined based on instructions pending in a plurality of processors. The controller determines adjustments that need to be made to the operating voltage and/or frequency to minimize the difference between the current power and the predicted power. An in-system reinforced learning mechanism is included to self-tune parameters of the controller.

A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Systems, methods, and apparatuses relating to circuitry to implement out-of-order access to a shared microcode sequencer by a clustered decode pipeline are described. In one embodiment, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, a fetch circuit to fetch a first block of instructions and send the first block of instructions to the first decode cluster for decoding, and fetch a second block of instructions younger in program order than the first block of instructions and send the second block of instructions to the second decode cluster for decoding, a microcode sequencer comprising a memory that stores a plurality of micro-operations, and an arbitration circuit to arbitrate access by the first decode cluster and the second decode cluster to a shared read port of the memory, wherein the arbitration circuit is to allow the second decode cluster decoding the second block of instructions access to the shared read port of the memory instead of the first decode cluster decoding the first block of instructions when an instruction of the second block of instructions has a number of corresponding micro-operations in the microcode sequencer below an arbitration threshold.

Methods and apparatus relating to branch prefetch mechanisms for mitigating frontend branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.

Pipeline-based techniques for system configuration management are provided. For example, a method comprises, in a pipeline-based system comprising a set of one or more pipelines, for a given one of the set of one or more pipelines, collecting a set of one or more configuration datasets respectively associated with a set of one or more elements of an information processing system, wherein each of the configuration datasets of the collected set of one or more configuration datasets is specific to the respective element of the information processing system from which it is collected; executing a set of one or more configuration checks on the set of one or more configuration datasets; receiving a set of one or more output results from the executed one or more configuration checks; and generating at least one report from the one or more output results.

Systems, methods, and apparatuses for power efficient generation of length markers for a variable length instruction set are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, an instruction cache, an instruction length decoder circuit, a predecode cache comprising a predecode bit, for each section of multiple sections of instruction data, that indicates when that section is identified as an end boundary of a variable length instruction, an incomplete decode table comprising a bit, for each proper subset of sections of instruction data, that indicates when that proper subset of sections has one or more invalid predecode bits in the predecode cache; and a fetch circuit to, for an incoming address of instruction data, perform a lookup in the instruction cache and the incomplete decode table, and, when there is a hit in the instruction cache for the instruction data at the incoming address and a hit in the incomplete decode table that indicates a proper subset of sections of the instruction data for the incoming address has one or more invalid predecode bits in the predecode cache, causes the instruction length decoder circuit to generate one or more predecode bits for the proper subset of sections of the instruction data for the incoming address that has the one or more invalid predecode bits.

Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.

Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.

A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).