Inserting a proxy read instruction in an instruction pipeline in a processor is disclosed. A scheduler circuit is configured to recognize when a produced value generated by execution of a producer instruction in the instruction pipeline will not be available through a data forwarding path to be consumed for processing of a subsequent consumer instruction. In this case, the scheduling circuit is configured to insert a proxy read instruction in the instruction pipeline to cause execution of an operation to generate the same produced value as was generated by previous execution of producer instruction in the instruction pipeline. Thus, the produced value will remain available in the instruction pipeline to again be available through a data forwarding path to an earlier stage of the instruction pipeline to be consumed by a consumer instruction, which may avoid a pipeline stall.

The invention relates to the technical field of microprocessors, in particular to a renaming method and system of fixed constant related instructions. The invention classifies the instructions in the decoder according to the characteristics of the instructions, and selects the instructions with fixed constants. In the renaming stage, the invention maps the source register and the destination register of such instructions to different fixed constant physical registers according to different fixed constants, updates the register renaming mapping tables SPEC_MAP and ARCH_MAP, and releases the physical registers corresponding to the fixed constant when the instruction is submitted, thereby realizing the function of the instruction. The invention classifies the instruction, and the fixed constant instruction does not need to enter the execution unit, but realizes the execution of the instruction through the renaming method, and the instruction execution efficiency is high.

A processor includes a first level register file, second level register file, and register file mapper. The first and second level register files are comprised of physical registers, with the first level register file more efficiently accessed relative to the second level register file. The register file mapper is coupled with the first and second level register files. The register file mapper comprises a mapping structure and register file mapper controller. The mapping structure hosts mappings between logical registers and physical registers of the first level register file. The register file mapper controller determines whether to map a destination logical register of an instruction to a physical register in the first level register file. The register file mapper controller also determines, based on metadata associated with the instruction, whether to write data associated with the destination logical register to one of the physical registers of the second level register file.

Techniques described herein may be utilized to serialise and de-serialise arithmetic circuits that are utilized in the execution of computer programs. The arithmetic circuit may be utilized to build a Quadratic Arithmetic Problem (QAP) that is compiled into a set of cryptographic routines for a client and a prover. The client and prover may utilize a protocol to delegate execution of a program to the prover in a manner that allows the client to efficiently verify the prover correctly executed the program. The arithmetic circuit may comprise a set of symbols (e.g., arithmetic gates and values) that is compressed to produce a serialised circuit comprising a set of codes, wherein the set of symbols is derivable from the set of codes in a lossless manner. Serialisation and de-serialisation techniques may be utilized by nodes of a blockchain network.

An embodiment of the present invention is directed to a Mainframe CI/CD design solution and pattern that provides a complete end to end process for Mainframe application. This enables faster time to market by performing critical SDLC processes, including build, test, scan and deployment in an automated fashion on a regular basis. An embodiment of the present invention is directed to a CI/CD approach that journeys from receiving requirements to final deployment. For any new application onboarding, teams may implement the CI/CD approach that may be customized per requirements of each LOB/Application.

Various embodiments are provided reusing an operand in an instruction set architecture (ISA) by one or more processors in a computing system. An instruction may specify that an operand register for a selected operand retain operand data used by a previous instruction. The operand data in the operand register may be reused by the instruction.

A processor identifies matches between a load operation and a plurality of more store operations based on an address vector that represents a combination of addresses targeted by the store operations. The address vector is used to identify a potential match between an address targeted by the load operation and at least one of the addresses targeted by the plurality of store operations. This allows the processor to quickly identify when there are no potential matches between the load operation and any of the plurality of store operations, thereby reducing overhead at the processor and improving overall processing efficiency.

A method and an apparatus for adjusting an instruction pipeline, a memory and a storage medium. The method for adjusting the instruction pipeline includes: receiving a move-type instruction, wherein the move-type instruction includes a target operand and a first source operand, and indicates to move a data of a source address indicated by the first source operand to a target address indicated by the target operand; receiving an object instruction located after the move-type instruction in an instruction sequence, wherein the object instruction includes an object source operand, indicating that an object operation is performed with a source address indicated by the object source operand; and replacing the object source operand in the object instruction with the first source operand of the move-type instruction to obtain a modified instruction, in response to the target operand of the move-type instruction being identify to the object source operand of the object instruction.

A very long instruction word (VLIW) processor that performs efficient processing including extended bits operations is provided. The VLIW processor includes an instruction control unit, a register file unit, and an instruction execution unit. The instruction execution unit includes a plurality of slots, and a state register arranged between the second slot and the third slot to transfer N-bit data between the second and third slots. The VLIW processor stores data output from the third slot into the state register and uses the data, and thus achieves efficient processing including bit-expanded operations, such as processing performed in response to instructions commonly used in image processing, image recognition, and other processing, while preventing scaling up of the circuit.

Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.