A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

An apparatus has processing circuitry for executing instructions and fetch circuitry for fetching the instructions for execution. When a branch instruction is encountered by the fetch circuitry, it determines subsequent instructions to be fetched in dependence on an initial branch direction prediction for the branch instruction made by branch prediction circuitry. Value prediction circuitry is used to maintain a predicted result value for one or more instructions, and dispatch circuitry maintains a record of pending instructions that have been fetched by the fetch circuitry and are awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry. When a given instruction whose predicted result value is maintained by the value prediction circuitry has a dependent instruction whose outcome is dependent on a result value of the given instruction, the dispatch circuitry nay be arranged to enable speculative execution of that dependent instruction using the predicted result value of the given instruction. Analysis circuitry is arranged, when the dependent instruction is the branch instruction, to detect a mispredict condition when an additional branch direction prediction for the branch instruction determined using the predicted result value for the given instruction is considered more accurate that the initial branch direction prediction, and the additional branch direction prediction differs to the initial branch direction prediction. On detection of the mispredict condition, a control signal is issued to indicate that the branch instruction has been mispredicted.

A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.

An apparatus and method are provided for controlling a change in instruction set. The apparatus has processing circuitry arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry. A program counter capability storage element is used to store a program counter capability used by the processing circuitry to determined a program counter value. The processing circuitry is arranged to employ a capability based operation to change the instruction set. In response to execution of at least one type of instruction to load an identified capability into the program counter capability storage element, the processing circuitry is arranged to invoke the capability based operation in order to perform a capability check operation in respect of the identified capability, and to cause the instruction set to be identified by an instruction set identifier field from the identified capability provided the capability check operation is passed.

A computer system is presented. The computer system comprises a memory system that stores data, a computer processor, and a memory access engine. The memory access engine is configured to: receive a first instruction of a computing process from the computer processor, wherein the first instruction is for accessing the data from the memory system; acquire at least a part of the data from the memory system based on the first instruction; and after the acquisition of the at least a first part of the data, transmit an indication to the computer processor to enable the computer processor to execute a second instruction of the computing process.

A computer system includes a dispatch stage configured to dispatch a plurality of instructions in a program order, and an issue stage configured to issue at least one instruction among the plurality of instructions. The computer system further includes an execution stage configured to execute the at least one instruction to generate a finish report and to determine the at least one instruction is one of an exception-free instruction or an exception instruction. In response to determining the exception-free instruction, a first finish report associated with the exception-free instruction is output to a completion stage. In response to determining the exception instruction, a second finish report associated with the exception instruction is output to an exception unit so as to halt output of the second finish report to the completion stage.

Retiring instructions out-of-order includes: receiving processor instructions comprising two or more and fewer than all processor instructions generated based on a program, where the processor instructions include a first instruction and a second instruction such that the first instruction precedes the second instruction in a program order of the program; receiving a start instruction that immediately precedes the processor instructions and indicates that the processor instructions are to be retired out-of-order; receiving a stop instruction immediately that succeeds the processor instructions and indicates a stop to out-of-order instruction retirement; and, in response to completing execution of the second instruction before completing execution of the first instruction, retiring the second instruction before retiring the first instruction.

In one embodiment, a method includes accessing a loaded but paused source process executable and disassembling the source process executable to identify a system call to be instrumented and an adjacent relocatable instruction. Instrumenting the system call includes building a trampoline for the system call that includes a check flag instruction at or near an entry point to the trampoline and two areas of the trampoline that are selectively executed according to results of the check flag instruction. Building a first area of the trampoline includes providing instructions to execute a relocated copy of the adjacent relocatable instruction and return flow to an address immediately following the adjacent relocatable instruction. Building a second area of the trampoline includes providing instructions to invoke at least one handler associated with executing a relocated copy of the system call and return flow to an address immediately following the system call.

An apparatus comprises processing circuitry to issue load operations to load data from memory. In response to a plural-register-load instruction specifying at least two destination registers to be loaded with data from respective target addresses, the processing circuitry permits issuing of separate load operations corresponding to the plural-register-load instruction. Load tracking circuitry maintains tracking information for one or more issued load operations. When the plural-register-load instruction is subject to an atomicity requirement and the plurality of load operations are issued separately, the load tracking circuitry detects, based on the tracking information, whether a loss-of-atomicity condition has occurred for the load operations corresponding to the plural-register-load instruction, and requests re-processing of the plural-register-load instruction when the loss-of-atomicity condition is detected.