This application discloses an exception handling method, which may be applied to a processor. The method includes: The processor calls a second function according to a call instruction of a first function, where the first function is a high-level language function, and the second function is a runtime function. When an exception occurs in a process of executing the second function, the processor executes a return operation of the second function, where the return operation of the second function includes restoring a status of a first register used when the second function is executed to a status before the first function calls the second function. The processor performs exception handling based on the status of the first register. The method can improve running performance of the processor.

Preventing the observation of the side effects of mispredicted speculative execution flows using speculation buffering. A microprocessor comprises one or more speculation buffers that are separated from and correspond to one or more conventional buffers. The microprocessor records first effects of one or more speculatively-executed instructions to the one or more speculation buffers, and records second effects of non-speculatively-executed instructions to the one or more conventional buffers. The microprocessor commits the first effects from the one or more speculation buffers to the one or more conventional buffers when the one or more speculatively-executed instructions that generated the first effects are committed, and discards the first effects from the one or more speculation buffers when the one or more speculatively-executed instructions are cancelled.

The present disclosure relates to the field of a multi-chip system, and provides an interrupt processing method, a master chip, a slave chip, and a multi-chip system. An interrupt processing method is applied to a master chip and includes: when an interrupt transport request sent by a slave chip through an interrupt line is detected, obtaining all current interrupt requests (irq_s_1-irq_s_N) of the slave chip, the interrupt request (irq_s_1_-irq_s_N) is generated by a first peripheral (4) of the slave chip; obtaining an interrupt subroutine corresponding to each of the interrupt requests (irq_s_1-irq_s_N), and processing the corresponding interrupt request (irq_s_1-irq_s_N) by using the interrupt subroutine. In the embodiments of the present disclosure, all the interrupt requests (irq_s_1-irq_s_N) of the slave chip are mapped to the master chip, so that the interrupt processing flow of the peripheral on the slave chip is simplified.

A computer system includes a dispatch stage configured to dispatch a plurality of instructions in a program order, and an issue stage configured to issue at least one instruction among the plurality of instructions. The computer system further includes an execution stage configured to execute the at least one instruction to generate a finish report and to determine the at least one instruction is one of an exception-free instruction or an exception instruction. In response to determining the exception-free instruction, a first finish report associated with the exception-free instruction is output to a completion stage. In response to determining the exception instruction, a second finish report associated with the exception instruction is output to an exception unit so as to halt output of the second finish report to the completion stage.

Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

A method includes receiving an input data at a FP arithmetic operating unit configured to perform a FP arithmetic operation on the input data. The method further includes determining whether the received input data generates a FP hardware exception responsive to the FP arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation. The method also includes converting a value of the received input data to a modified value responsive to the determining that the received input data generates the FP hardware exception, wherein the converting eliminates generation of the FP hardware exception responsive to the FP arithmetic operation on the input data.

There is provided execution circuitry. Storage circuitry retains a stored state of the execution circuitry. Operation receiving circuitry receives, from issue circuitry, an operation signal corresponding to an operation to be performed that accesses the stored state of the execution circuitry from the storage circuitry. Functional circuitry seeks to perform the operation in response to the operation signal by accessing the stored state of the execution circuitry from the storage circuitry. Delete request receiving circuitry receives a deletion signal and in response to the deletion signal, deletes the stored state of the execution circuitry from the storage circuitry. State loss indicating circuitry responds to the operation signal when the stored state of the execution circuitry is not present and is required for the operation by indicating an error. In addition, there is provided a data processing apparatus comprising issue circuitry to issue an operation to execution circuitry. The execution circuitry stores a stored state that is accessed during performance of the operation and error detecting circuitry detects an indication of an error from the execution circuitry that the stored state is required for performance of the operation and that the stored state has been deleted.

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

A method of processing exceptions in an exception-driven computing-based system that operates in either initialisation mode or exception-driven mode. The method includes, upon detecting an exception has occurred, causing the processor to execute exception handling instructions. When the system is operating in initialisation mode the exception handling instructions invoke a first exception handler that causes a main register set to be saved before processing the exception and restored after processing the exception, and when the system is operating in exception-driven mode the exception handling instructions invoke a second exception handler that does not cause the main register set to be saved and restored. In some examples, the exception handling instructions are initially configured to invoke the first exception handler and are dynamically updated when the system switches from initialisation mode to exception-driven mode to invoke the second exception handler.