Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.

This disclosure describes methods, devices, systems, and procedures in a computing system for capturing a configuration state of an operating system executing on a central processing unit (CPU), and offloading resource-related tasks, based on the configuration state, to a resource management unit such as a system-on-chip (SoC). The resource management unit identifies a status of each resource based on the captured configuration state of the operating system. The resource management unit then processes tasks associated with the status of the resources, such as modifying a clock rate of a clocked component in the computing system. This can alleviate the CPU from processing those tasks thereby improving overall computing system performance and dynamics.

An instruction processing apparatus is disclosed. The instruction processing apparatus includes: a selector is configured to parse out a command type and a buffer identifier from a command, provide received data and the buffer identifier to a parser if the command type is configuration, and provide the received data and the buffer identifier to an operation circuit if the command type is execution; the parser is configured to parse out an instruction sequence from the data, store the instruction sequence into an instruction buffer corresponding to the buffer identifier, and store an operand of each instruction into a register file; and the operation circuit is configured to drive the instruction buffer to execute each instruction and generate a control signal, and trigger a plurality of execution units to perform operations based on received control signals and operands. The apparatus may be dedicated to processing various neural network applications.

A graphics pipeline cache reconstruction operation is implemented to reconstruct one or more graphics pipeline caches for a current client gaming session based on one or more pipeline structures. The pipeline structures each represent a graphical object rendered during a respective previous client gaming session and are used to reconstruct one or more graphics pipeline caches that include graphics pipeline cache objects related to the graphical objects of the pipeline structures. These graphics pipeline cache objects are used to initialize one or more graphics pipelines used to render the graphical objects in a gaming application for a current client gaming session.

In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.

A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

A scalable Internet of Things (IoT) system may include multiple instances of an IoT manager, each instance respectively configured to connect to a respective edge system of multiple edge systems. The IoT system may further include a containerized system configured to allow any instance of the IoT manager to deploy data pipelines to any edge system of the multiple edge systems in delta communications. Any instance of the IoT manager may send a change message to any edge system via a publish/subscribe notification method. In some examples, a centralized IoT manager may form a secure communication with an edge system, synchronize an object model with an edge object model for the edge system, and maintain the edge system using delta change communications. The IoT system may facilitate any instance of the IoT manager to subscribe a communication channel with an associated edge system for receiving update notification.

A supervisory control system provides power management in an electronic device by providing timeout periods for a hardware component to lower levels of the operating system such as a power management arbitrator and/or a hardware interface controller. The power management arbitrator and/or hardware interface controller transition at least a portion of a hardware component to a lower-power state based on monitored activity information of the hardware component. The supervisory control system may further provide wakeup periods to the power management arbitrator and/or a hardware interface controller to determine whether the hardware component should be transitioned to a higher-power state at the end of the wakeup period if the hardware component satisfies a transition condition.

A fault tolerant system includes a primary virtual machine and a secondary virtual machine. The primary virtual machine includes a synchronizing information generator and a first interrupt blocker. The synchronizing information generator executes bytecode and outputs synchronizing information based on information related to the executed bytecode. The first interrupt blocker blocks an interrupt inputted from an external location. The secondary virtual machine includes a synchronous execution unit that executes the bytecode based on the synchronizing information and a second interrupt blocker that blocks the interrupt. When the interrupt is acquired, the synchronizing information generator executes the bytecode based on the interrupt. The first interrupt blocker outputs the interrupt to the synchronizing information generator when the interrupt is inputted during execution of an instruction, included in the bytecode, to accept the interrupt.

Systems, methods, and other embodiments associated with associated with unified pipeline flow with common and phase-specific paths are described. In one embodiment, a method includes accepting, through a graphical user interface, a setting of a phase-specific link type for a link between nodes of a pipeline, wherein the phase-specific link type indicates that the link is associated with a particular phase; accepting, through the graphical user interface, a selection to execute the pipeline for the phase; parsing the pipeline to determine an execution set of nodes for execution in the phase based on the nodes being connected with links having either the link type or a default link type common to all phases; and executing the pipeline for the phase by executing the execution set of nodes, and not executing nodes not included in the set of nodes.