Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Disclosed herein are an apparatus for preloading data in a distributed computing environment and a method using the same. The method includes selecting a local preloading target that each of multiple computers connected over a network is to preload into the local memory thereof, registering a local preloading task corresponding to the local preloading target in local preloading metadata, and asynchronously starting the local preloading task at a preset time based on the local preloading metadata. The local preloading metadata is stored in a page other than the page in which remote preloading metadata for managing a remote preloading task is stored.

An apparatus is described. The apparatus includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

A method for image processing is provided. The method may include: obtaining a plurality of frames, each of the plurality of frames comprising a plurality of pixels; determining, based on the plurality of frames, whether a current frame of the plurality of frames comprises a moving object; in response to determining that the current frame includes no moving object, obtaining a first count of frames, and generating a target image by superimposing the first count of frames; in response to determining that the current frame includes a moving object, obtaining a second count of frames, and generating the target image by superimposing the second count of frames.

Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

Embodiments described herein are directed to a programming language trigger mechanism. The trigger mechanism is a small piece of code that a software developer utilizes in a computer program. The trigger mechanism enables computing operations or tasks to be performed asynchronously and in a parallel fashion. In particular, logic (e.g., operations or tasks) associated with the trigger mechanism are provided to a plurality of resources for processing in parallel. Each resource asynchronously processes the task provided thereto and asynchronously provides the result. The results are asynchronously returned as an enumeration. The enumeration enables the software developer to enumerate through the returned elements as a simple stream of results as they are calculated.

An apparatus for managing a resource includes a buffer memory; and a processor configured to store, when target data for each of processes is acquired, the acquired target data in the buffer memory, the processes occurring asynchronously and periodically and being assigned degrees of priority, and assign a shared resource to some of the processes for which the target data is stored in the buffer memory in descending order of the priority at every predetermined timing, the shared resource being usable for each of the processes.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

The technology disclosed herein enables a processor that processes instructions synchronously in accordance with a processor clock to identify a first instruction specifying an asynchronous operation to be processed independently of the processor clock. The asynchronous operation is performed by an asynchronous execution unit that executes the asynchronous operation independently of the processor clock and generates at least one result of the asynchronous operation. A synchronous execution unit executes, in parallel with the execution of the asynchronous operation by the asynchronous execution unit, one or more second instructions specifying respective synchronous operations. Responsive to determining that the asynchronous execution unit has generated the at least one result of the asynchronous operation, the processor receives the at least one result of the asynchronous operation.