A browser can include a script monitoring module to monitor executing scripts and log the initiating scripts for API calls or other monitored actions. In some embodiments, the script monitoring module overwrites built-in or web APIs in the browser with versions of the APIs that allow the script monitoring module to identify the scripts calling the APIs. Using the script monitoring module, the script initiating an action (such as an API call) can be identified using features of the browser. In some embodiments, all actions may be monitored in this way, permitting the tracking and analysis of scripts and full analysis of interaction between such scripts on the webpage and with the browser.

In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.

An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

A calculation apparatus is included in a combined processing apparatus, which also includes a general interconnection interface and other processing apparatuses. The calculation apparatus interacts with other processing apparatuses to jointly complete calculations specified by users. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to a device and other processing apparatuses and is used for storing data of the device and data of other processing apparatuses. Operational efficiency of calculation of every kind of data processing fields including an artificial intelligence field can be improved, thereby decreasing overall overheads and cost of the calculation.

A request to initiate a launch procedure of a compute instance at a virtualization host configured to access a remote storage device over a network is received. A memory buffer of the host is allocated as a write-back cache for use during a portion of the launch procedure. In response to a write request directed to remote storage during the portion of the launch procedure, the write payload is stored in the buffer and an indication of fulfillment of the write is provided independently of obtaining an acknowledgement that the payload has been propagated to the remote storage. Subsequent to the portion of the launch procedure, payloads of other write requests are transmitted to the remote storage device.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an asynchronous packet network; a plurality of configurable circuits arranged in an array, each configurable circuit coupled to the asynchronous packet network and adapted to perform a plurality of computations; and a dispatch interface circuit adapted to partition the plurality of configurable circuits into one or more separate partitions of configurable circuits and to load one or more computation kernels into each partition of configurable circuits. The dispatch interface circuit may load balance across the partitions of configurable circuits by starting threads for execution in the partition having the highest number of available thread identifiers. The dispatch interface may also assert a partition enable signal to merge the one or more separate partitions and assert a stop signal to all configurable circuits of the one or more separate partitions of configurable circuits.

A method for image processing is provided. The method may include: obtaining a plurality of frames, each of the plurality of frames comprising a plurality of pixels; determining, based on the plurality of frames, whether a current frame of the plurality of frames comprises a moving object; in response to determining that the current frame includes no moving object, obtaining a first count of frames, and generating a target image by superimposing the first count of frames; in response to determining that the current frame includes a moving object, obtaining a second count of frames, and generating the target image by superimposing the second count of frames.

Devices and techniques for asynchronous pipeline merging are described herein. An apparatus, includes a memory controller, which includes merge circuitry; where the memory controller chiplet is configured to perform operations including those to: perform a bitwise logical operation on a first logging bit vector and a second logging bit vector to obtain a result vector, wherein the first logging bit vector is associated with a first pipeline and the second logging bit vector is associated with a second pipeline, and wherein bits in respective index positions of the first and second logging bit vectors represent transactions; select a completed transaction from the result vector using a round-robin technique; and forward the completed transaction from the set of completed transactions to an output pipeline.

Techniques are described herein that are capable of reducing latency of changing an operating state of a processor from a low-power state to a normal-power state. For example, providing a notification from a hardware system to the processor or receiving the notification at the processor, indicating that a transaction layer packet will be provided to the processor at a future time, may trigger the processor to change the operating state from the low-power state to the normal-power state. In another example, receipt of a transaction layer packet at the processor from a hardware system may trigger the processor to change the operating state from the low-power state to the normal-power state.

To synchronize operations of a computing system, a new type of synchronization barrier is disclosed. In one embodiment, the disclosed synchronization barrier provides for certain synchronization mechanisms such as, for example, “Arrive” and “Wait” to be split to allow for greater flexibility and efficiency in coordinating synchronization. In another embodiment, the disclosed synchronization barrier allows for hardware components such as, for example, dedicated copy or direct-memory-access (DMA) engines to be synchronized with software-based threads.