A datapath pipeline which uses replicated logic blocks to increase the throughput of the pipeline is described. In an embodiment, the pipeline, or a part thereof, comprises a number of parallel logic paths each comprising the same logic. Input register stages at the start of each logic path are enabled in turn on successive clock cycles such that data is read into each logic path in turn and the logic in the different paths operates out of phase. The output of the logic paths is read into one or more output register stages and the logic paths are combined using a multiplexer which selects an output from one of the logic paths on any clock cycle. Various optimization techniques are described and in various examples, register retiming may also be used. In various examples, the datapath pipeline is within a processor.

A processor architecture arrangement for emulated shared memory (ESM) architectures is disclosed. The arrangement has a number of multi-threaded processors, each provided with an interleaved inter-thread pipeline and a plurality of functional units for carrying out arithmetic and logical operations on data. The pipeline has at least two operatively parallel pipeline branches. The first pipeline branch includes a first sub-group of the plurality of functional units, such as ALUs (arithmetic logic unit) for carrying out integer operations. The second pipeline branch includes non-overlapping subgroup of the plurality of functional units, such as FPUs (floating point unit) for carrying out floating point operations. One or more of the functional units of at least the second sub-group are located operatively in parallel with the memory access segment of the pipeline.

Described herein is a merged data path unit that has elements that are configurable to switch between different instruction types. The merged data path unit is a pipelined unit that has multiple stages. Between different stages lie multiplexor layers that are configurable to route data from functional blocks of a prior stage to a subsequent stage. The manner in which the multiplexor layers are configured for a particular stage is based on the instruction type executed at that stage. In some implementations, the functional blocks in different stages are also configurable by the control unit to change the operations performed. Further, in some implementations, the control unit has sideband storage that stores data that “skips stages.” An example of a merged data path used for performing a ray-triangle intersection test and a ray-box intersection test is also described herein.

Various systems and methods for implementing intent-driven power management are described herein. A system includes: a power monitoring unit to collect real-time telemetry of a processor on a compute node; and a power level controller to: receive a power intent for execution of an application on the compute node; configure a power level of the processor of the compute node based on the power intent, the processor to execute the application; set an initial execution priority of the application on the compute node based on the power intent; and modify the initial execution priority based on the power intent and the real-time telemetry of the compute node.

Various systems and methods for implementing reputation management and intent-based security mechanisms are described herein. A system for implementing intent-driven security mechanisms, configured to: determine, based on a risk tolerance intent related to execution of an application on a compute node, whether execution of a software-implemented operator requires a trust evaluation; and in response to determining that the software-implemented operator requires the trust evaluation: obtain a reputation score of the software-implemented operator; determine a minimum reputation score from the risk tolerance intent; compare the reputation score of the software-implemented operator to the minimum reputation score; and reject or permit execution of the software-implemented operator based on the comparison

Various systems and methods for implementing computational storage are described herein. An orchestrator system is configured to: receive, at the orchestrator system, a registration package, the registration package including function code, a logical location of input data for the function code, and an event trigger for the function code, the event trigger set to trigger in response to when the input data is modified; interface with a storage service, the storage service to monitor the logical location of the input data and notify a location service when the input data is modified; interface with the location service to obtain a physical location of the input data, the location service to resolve the physical location from the logical location of the input data; and configure the function code to execute near the input data

Various systems and methods for implementing intent-based cluster administration are described herein. An orchestrator system includes: a processor; and memory to store instructions, which when executed by the processor, cause the orchestrator system to: receive, at the orchestrator system, an administrative intent-based service level objective (SLO) for an infrastructure configuration of an infrastructure; map the administrative intent-based SLO to a set of imperative policies; deploy the set of imperative policies to the infrastructure; monitor performance of the infrastructure; detect non-compliance with the set of imperative policies; and modify the administrative intent-based SLO to generate a revised set of imperative policies that cause the performance of the infrastructure to be compliant with the revised set of imperative policies.

Various systems and methods for reactive intent-driven end-to-end (E2E) orchestration are described herein. An orchestrator system, includes a processor; and memory to store instructions, which when executed by the processor, cause the system to: receive, at the orchestrator system, an intent-based service level agreement (SLA) for execution of a series of tasks on a plurality of compute nodes; calculate, based on the intent-based SLA, intermediate latency thresholds corresponding to each task of the series of tasks; calculate slack estimates based on the latency thresholds and real-time telemetry of the plurality of compute nodes or real-time telemetry of connections between the plurality of compute nodes; monitor execution of the series of tasks on the plurality of compute nodes; and perform a corrective action in response to determining that the execution of the series of tasks is predicted to exceed one of the intermediate latency thresholds

Various systems and methods for implementing intent-based orchestration in heterogenous compute platforms are described herein. An orchestration system is configured to: receive, at the orchestration system, a workload request for a workload, the workload request including an intent-based service level objective (SLO); generate rules for resource allocation based on the workload request; generate a deployment plan using the rules for resource allocation and the intent-based SLO; deploy the workload using the deployment plan; monitor performance of the workload using real-time telemetry; and modify the rules for resource allocation and the deployment plan based on the real-time telemetry.

A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.