The illustrative embodiments provide a method, system, and computer program product. In an embodiment, a method includes receiving a set of Pauli observables. In an embodiment, a method includes initializing a measurement basis, the measurement basis comprising a set of Pauli bases equivalent to a number of qubits of a quantum processor. In an embodiment, a method includes creating a list of a set of Bell basis candidates, each of the set of Bell basis candidates configured to measure at least one of the set of Pauli observables. In an embodiment, a method includes selecting a Bell basis candidate from the set of Bell basis candidates. In an embodiment, a method includes reconfiguring the measurement basis to replace a subset of the set of Pauli bases with the selected Bell basis candidate.

A graphics processing system for operation with a data store, comprising: one or more processing units for processing tasks; a check unit operable to form a signature which is characteristic of an output from processing a task on a processing unit; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is operable to process each task first and second times at the one or more processing units so as to, respectively, generate first and second processed outputs, the graphics processing system being configured to: write out the first processed output to the data store; read back the first processed output from the data store and form at the check unit a first signature which is characteristic of the first processed output as read back from the data store; form at the check unit a second signature which is characteristic of the second processed output; compare the first and second signatures at the fault detection unit; and raise a fault signal if the first and second signatures do not match.

A control system is for controlling safety-critical processes, non-safety-critical processes, and/or installation components. The control system includes: at least one control unit configured to control non-safety-critical processes and/or non-safety-critical installation components, at least one safety control unit for controlling safety-critical processes and/or safety-critical installation components, and at least one input/output unit connected to the first control unit via an internal input/output bus. The control system is configured to act as communication master or as communication minion or as both in a pool having other devices that is connected via field bus, and to that end, the control system includes a master communication coupler and a minion communication coupler. The control system is modularly configurable. At least the safety control unit includes respective subunits with master functionality and subunits with minion functionalities.

In accordance with certain techniques, at a first processor of a dual-processor storage system, a change in an initial logical unit corresponding to a storage area in a physical storage device of the storage system is detected. Based on the change in the initial logical unit, a plurality of update operations to be performed on a mapped logical unit driver mapping a plurality of initial logical units including the initial logical unit to a plurality of mapped logical units are determined. An indication of the plurality of update operations is sent to a second processor of the storage system, to cause the second processor to perform the plurality of update operations on a peer mapped logical unit driver associated with the mapped logical unit driver. Accordingly, there is improved performance of the dual-processor storage system.

An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

A computer-implemented method for numerical solution of a geometric programming problem is described, including the computer-implemented steps of: reformulating the geometric programming problem as an equivalent generalized geometric programming optimization problem with only linear constraints, and solving the equivalent generalized geometric programming optimization problem by vector processing, including determining by computer-implemented numerical computation a solution for an unconstrained objective function whose independent vector variable is the generalized geometric programming conjugate dual of a primal decision vector variable of the geometric programming problem, and includes a variable linear combination of fixed vectors enabling the vector processing. Also described are computer-readable storage devices, computer program products, and computer systems for such numerical solution methodology.

A graphics processing system for operation with a data store, comprising: one or more processing units for processing tasks; a check unit operable to form a signature which is characteristic of an output from processing a task on a processing unit; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is operable to process each task first and second times at the one or more processing units so as to, respectively, generate first and second processed outputs, the graphics processing system being configured to: write out the first processed output to the data store; read back the first processed output from the data store and form at the check unit a first signature which is characteristic of the first processed output as read back from the data store; form at the check unit a second signature which is characteristic of the second processed output; compare the first and second signatures at the fault detection unit; and raise a fault signal if the first and second signatures do not match.

Methods for performing computations using a lattice of interconnected devices are described. The lattice is programmed to perform the computation by choosing a specific logic function for each device. An energy penalty is attributed to each device when the associated input and output bits do not satisfy a truth table of the logic function of the device. Input data is inserted on the boundaries of the lattice by attributing energy penalties to the input and output bits at the boundaries when the states of those bits do not match the input data. The energy in the lattice is lowered for the lattice to reach a configuration where all gate and boundary constraints are satisfied. The result of the computation is read from the output data encoded in the states of the bits of the devices at the boundaries of the lattice which are not already fixed by the input data.

A graphics processing system for operation with a data store includes processing units for processing tasks. A check unit forms a signature which is characteristic of an output from processing a task on a processing unit, and a fault detection unit compares signatures formed at the check unit. The graphics processing system processes each task first and second times at the processing units so as to generate first and second processed outputs. The graphics processing system write outs the first processed output to the data store, reads back the first processed output from the data store and forms at the check unit a first signature characteristic of the first processed output as read back from the data store; forms at the check unit a second signature characteristic of the second processed output, compares the first and second signatures at the fault detection unit, and raises a fault signal if the signatures do not match.

An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.