In one embodiment, a processor includes: a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage to a memory of a software-provided list of processor state information; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of a data table in the memory. Other embodiments are described and claimed.

System and method for reducing latency for nested virtual machines. An example method may include: running, by a host computer system, a hypervisor managing a first virtual machine associated with a first virtual processor (vCPU) implemented by a first processing thread, wherein the first virtual machine manages a second virtual machine; creating, by the hypervisor, a second processing thread implementing a second vCPU associated with the second virtual machine; and responsive to receiving an interrupt directed to the second virtual machine, causing, by the hypervisor, the second processing thread to process the interrupt.

An image signal processor includes a command queue circuit, an image processing engine and an interrupt control circuit. The command queue circuit stores a plurality of commands and sequentially provides the plurality of commands one by one. Each command of the plurality of commands includes an interrupt control value corresponding to each image unit of a plurality of image units. The plurality of commands are received from a control processor. The image processing engine receives the plurality of image units and sequentially processes the plurality of image units based on the plurality of commands sequentially provided from the command queue circuit. The interrupt control circuit receives the interrupt control value from the command queue circuit, determines one or more output interrupt event signals among a plurality of interrupt event signals based on the interrupt control value and generates an interrupt signal based on the output interrupt event signals.

A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

Disclosed are various embodiments for decreasing the amount of time spent processing interrupts by switching contexts in parallel with processing an interrupt. An interrupt request can be received during execution of a process in a less privileged user mode. Then, the current state of the process can be saved. Next, a switch from the less privileged mode to a more privileged mode can be made. The interrupt request is then processed while in the more privileged mode. Subsequently or in parallel, and possibly prior to completion of the processing the interrupt request, another switch from the more privileged mode to the less privileged mode can be made.

Instruction processing is performed for an instruction. The instruction is configured to perform a plurality of functions, in which a function of the plurality of functions is to be performed in a plurality of processing phases. A processing phase is defined to store up to a select amount of data. The select amount of data is based on the function to be performed. At least one function of the plurality of functions has a different value for the select amount of data than at least one other function. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of a select function. Based on determining that the store into the designated area occurred, an interrupt is presented, and based on determining that the store into the designated area did not occur, instruction processing is continued.

According to certain embodiments, a system includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including executing a software process of a secondary instance, the secondary instance running in parallel with a primary instance and associated with a plurality of cores including a bootstrap core, registering a non-maskable interrupt for the bootstrap core in the secondary instance, determining whether the secondary instance is in a fault state, wherein, if the secondary instance is in the fault state, halting the plurality of cores associated with the secondary instance, without impact to the primary instance, and recovering the bootstrap core by switching a context of the bootstrap core from the secondary instance to the primary instance via the non-maskable interrupt.

Techniques of adapting an interrupt escalation path are implemented in hardware. An interrupt controller receives, from a physical thread of the processor core, a request to adapt, in an event assignment data structure, an escalation path for a specified event source, where the escalation path includes a pointer to a first event notification descriptor. The interrupt controller reads an entry for the physical thread in an interrupt context data structure to determine a virtual processor thread running on the physical thread. Based on the virtual processor thread determined from the interrupt context data structure, the interrupt controller accesses an entry in a virtual processor data structure to determine a different second event notification descriptor to which escalations are to be routed. The interrupt controller updates the pointer in the event assignment data structure to identify the second event notification descriptor, such that the interrupt escalation path is adapted.

Embodiments of the present disclosure relate to a method for running an application, an electronic device, and a computer program product. The method includes determining, based on historical data associated with running of the application, a target time period and a computing resource to be used for running the application within the target time period, a load rate associated with the computing resource being higher than a threshold load rate in the target time period. The method further includes determining an interruption tolerance of the application based on a type of the application, determining costs for running the application by a plurality of types of virtual machines and determining a target type from the plurality of types based on the costs and the computing resource, to cause the application to be run by a virtual machine of the target type.

Packet routing within a multi-chip processing system is shown. A first chip has a first interconnect bus, and a first microprocessor coupled to the first interconnect bus. The first interconnect bus has a first routing register. When the first microprocessor operates the first chip as a source node to output a packet to be transferred to a destination node, routing information indicating a routing path from the source node to the destination node is written into the first routing register and then loaded from the first routing register to a header of the packet. While being transferred within the multi-chip processing system from the source node to the destination node, the packet is guided along the routing path indicated in the routing information carried in the header of the packet.