An apparatus and method are provided for handling prediction information. The apparatus has processing circuitry for performing data processing operations in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction comprising a sequence of instructions. Prediction circuitry is used to generate predictions in relation to instruction flow changing instructions, and prediction storage is provided to store a plurality of items of prediction information that are referenced by the prediction circuitry when generating the predictions. The items of prediction information maintained by the prediction storage change based on the instructions being executed by the processing circuitry. A recovery storage is activated by the transactional memory support circuitry at a transaction start point to store a restore pointer identifying a chosen location in the prediction storage. Between the transaction start point and the transaction end point, the recovery storage receives any item of prediction information removed from the prediction storage that was present in the prediction storage at the transaction start point. In response to the transaction being aborted, the restore pointer is used in order to discard from the prediction storage any items of prediction information added to the prediction storage after the transaction start point, and in addition any items of prediction information stored in the recovery storage are stored back into the prediction storage. This can significantly improve prediction accuracy in systems that may need to retry transactions due to a transaction abort, without requiring the entire prediction storage state to be captured at the transaction start point.

Operating a data distribution including a data distribution module and a plurality of host-bus adapters coupled to the data distribution module can include defining a coherent group that includes a set of members that includes the plurality of host-bus adapters; providing a group-coherent memory area in each of the set of members; and initiating a one-to-all broadcast message from a one of the plurality of host-bus adapters to all of the set of members when the one of the plurality of host-bus adapters requests a write to its local group-coherent memory area. The group-coherent memory area in each of the set of members is physically mirrored with a temporal coherence and no semaphores or access enables are required to achieve the temporal coherence of the coherent group.

An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.

A method for operating a multi-transaction memory system, the method includes: storing Logical Block Address (LBA) information changed in response to a request from a host and a transaction identification (ID) of the request into one page of a memory block; and performing a transaction commit in response to a transaction commit request including the transaction ID from the host, wherein the performing of the transaction commit includes: changing a valid block bitmap in a controller of the multi-transaction memory system based on the LBA information.

An apparatus and method are provided for handling transactions in a system employing transactional memory. The apparatus has processing circuitry for performing data processing in response to instructions, and transactional memory support circuitry for supporting execution of a transaction within a thread of data processing by the processing circuitry. The transaction comprises a sequence of instructions executed speculatively and for which the processing circuitry prevents commitment of results of those instructions until the transaction has reached a transaction end point. The transactional memory support circuitry comprises abort event detection circuitry that causes execution of the transaction to be aborted when an abort event is detected before the transaction has reached the transaction end point, and which causes abort status information to be stored for later reference when determining whether to retry execution of the transaction.

Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

In an apparatus with transactional memory support circuitry, for a first type of transaction started using a first type of transaction start instruction, commitment of results of instructions executed speculatively following the first type of transaction start instruction are prevented until a transaction end instruction is reached. An abort is triggered when a conflict is detected between an address of a memory access from another thread and the addresses tracked for the transaction. For a second type of transaction started using a second type of transaction start instruction, an address of the read operation is marked as trackable whilst an address of a write operation is omitted from being marked as trackable. This allows an apparatus that supports transactional memory to also be used for multi-word address watching.

Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.

The techniques described herein may provide techniques to detect, categorize, and diagnose synchronization issues that provide improved performance and issue resolution. For example, in an embodiment, a method may comprise detecting occurrence of synchronization performance problems in software code, when at least some detected synchronization performance problems occur when a contention rate for software locks is low, determining a cause of the synchronization performance problems, and modifying the software code to remedy the cause of the synchronization performance problems so as to improve synchronization performance of the software code.

In an embodiment, a processor comprises an atomic predictor circuit to predict whether or not an atomic operation will complete successfully. The prediction may be used when a subsequent load operation to the same memory location as the atomic operation is executed, to determine whether or not to forward store data from the atomic operation to the subsequent load operation. If the prediction is successful, the store data may be forwarded. If the prediction is unsuccessful, the store data may not be forwarded. In cases where an atomic operation has been failing (not successfully performing the store operation), the prediction may prevent the forwarding of the store data and thus may prevent a subsequent flush of the load.