Apparatuses, systems, and techniques to detect faults in processing pipelines are described. One accelerator circuit includes a fixed-function circuit that performs an operation corresponding to a layer of a neural network. The fixed-function circuit includes a set of homogeneous processing units and a fault scanner circuit. The fault scanner circuit includes an additional homogeneous processing unit to scan each processing unit of the set for functional faults in a sequence.

A control device includes a first controller, a second controller and a storage. The first controller performs safety control for a drive device. The second controller performs standard control for the drive device. The storage is accessible by both the first and second controllers and includes a first storage area and a second storage area. The first storage area stores data involved with the safety control, and the second storage area stores data involved with the standard control. The first controller accesses both the first storage area and the second storage area, and the second controller accesses the second storage area but is restricted from accessing the first storage area.

A safety module having a plurality of microcontrollers receives an analog input and determines a value of the analog input. The microcontrollers each determine a respective ternary state of the device by identifying, from three candidate ranges of values, a range of values in which the value falls, wherein at least two of the plurality of microcontrollers uses different candidate ranges of values, determining, based on the identified range, a ternary state corresponding to the range, and assigning the determined ternary state as the respective ternary state. The safety module determines whether the ternary states from the two microcontrollers map to a fault state, and, where they do, cause a command a command to be output to the device to enter a safe state.

A method includes, storing a set of valid codewords including: a first valid functional codeword representing a functional state of a controller subsystem; a first valid fault codeword representing a fault state of the controller subsystem and characterized by a minimum hamming distance from the first valid functional codeword; a second valid functional codeword representing a functional state of a controller; and a second valid fault codeword representing a fault state of the controller; in response to detecting functional operation of the controller subsystem, storing the first valid functional codeword in a first memory; in response to detecting a match between contents of the first memory and the first valid functional codeword, outputting the second valid functional codeword; in response to detecting a mismatch between contents of the first memory and every codeword in the first set of valid codewords, outputting the second valid fault codeword.

A parallel processing system includes at least three parallel processors, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

Various embodiments may include methods and systems for reconfiguring memory channel routing within a system-on-a-chip (SoC). A method may include obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC. The method may further include storing the first error information in non-volatile memory that is read upon booting of the SoC, and rebooting the SoC including the first memory channel. The method may further include configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot.

A programmable electronic power regulator includes a power module for controlling an actuator, a control module for actuating the power module, and an internal monitoring module for transferring the control module to an emergency operation. The internal monitoring module is configured to monitor a system state, detect a critical operating state, and output an error signal. The control module comprises: a basic controller, which is configured to output a power module control signal, and in which functions for open- and closed-loop control of the actuator are implemented, which are required for an emergency operation in a critical operating state; an additional controller, in which functions that are not needed for emergency operation are implemented; and a controller disconnection point, which connects the basic controller with the additional controller via a control connection, and which is configured to at least partially disconnect the control connection upon receipt of the error signal.

An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster. In some implementations, the power management processor receives, from a system controller external to the plurality of processing clusters, a first power allocation for the first processing cluster.

A method for determining a faulty computing core in a multi-core processor and an electronic device are provided. The method is applied to an electronic device configured with a multi-core processor. The multi-core processor is integrated with a plurality of computing cores, the plurality of computing cores are independent of each other, and the plurality of computing cores include a first computing core. The method includes: determining a computing core corresponding to each of N running exceptions, where the running exception is caused by an exception that occurs when any computing core in the plurality of computing cores executes the program instructions (301); and when a quantity of running exceptions corresponding to the first computing core in the N running exceptions is greater than or equal to M, determining that the first computing core is a faulty computing core, where M is a preset value (303).

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.