An information processing system includes: a first system that includes a group of arithmetic units, a controller, and an external device; and a second system configured to execute calculation which is the same as calculation executed in the first system and compare calculation results to each other, wherein the controller is configured to: stop a plurality of arithmetic units when it is detected that an output request to the external device is output from one or more arithmetic units among the plurality of arithmetic units that execute first calculation in the group of arithmetic units, the plurality of arithmetic units including one or more arithmetic units that does not output the output request, transmit first comparison target data including a value output in response to the output request to the second system, and instruct the stopped one or more arithmetic units to execute second calculation.

A resource processing method and device for a multi-controller system are provided. The method includes that: when a controller in the multi-controller system may not sense existence of a peer controller, the controller judges whether the peer controller loads a first resource pool according to a first use tag stored in the first resource pool previously loaded by the peer controller.

A failure detection circuit for a motor vehicle electronic computer, including: a main microcontroller having at least two microcontroller cores configured to execute the same instructions in parallel, and at least one first software module providing a critical function of a motor vehicle. The first software module includes a predetermined input point and a predetermined output point a supervision microcontroller and a synchronous communication interface for coupling the main microcontroller and the supervision microcontroller so as to enable mutual supervision. The detection circuit makes it possible to detect systematic and random failures.

A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship between progress of the first state machine to a first state machine state and progress to a second state. The predetermined temporal relationship may require the first state machine to progress to the first state machine state before the progress to the second state. The current state of the temporal relationship state machine may be one of a first temporal relationship state and a second temporal relationship state. The second state may be a second state machine state of the first state machine. The second state may be a second state machine state of a second state machine.

According to a first aspect of the present disclosure, an electronic device is provided, comprising: an attack detection unit arranged to detect one or more attacks on the electronic device; a countermeasure unit arranged to apply countermeasures against the attacks detected by the attack detection unit; a threat level determination unit arranged to determine a threat level corresponding to the attacks detected by the attack detection unit; wherein the countermeasure unit is further arranged to activate one or more specific ones of said countermeasures in dependence on the threat level determined by the threat level determination unit. According to a second aspect of the present disclosure, a corresponding method of protecting an electronic device is conceived. According to a third aspect of the present disclosure, a corresponding computer program product is provided.

A supervisory hardware device in a processor core detects a flush instruction that, when executed, flushes content of one or more general purpose registers (GPRs) within the processor core. The content of the one or more GPRs is moved to a history buffer (HB) and an instruction sequencing queue (ISQ) within the processor core, where the content includes data, an instruction tag (iTag) that identifies an instruction that generated the data, and error correction code (ECC) bits for the data. In response to receiving a restore instruction, the supervisory hardware device error checks the data in the ISQ using the ECC bits stored in the ISQ. In response to detecting an error in the data in the ISQ, the supervisory hardware device sends the data and the ECC bits from the ISQ to an ECC scrubber to generate corrected data, which is restored into the one or more GPRs.

In an approach to identifying a source of a time-of-day network error, one or more computers increment a first counter and a second counter on each of one or more computer processors simultaneously. The one or more computers determine whether an error is detected in the one or more computer processors. In response to determining the error is detected, the one or more computers freeze the second counter on the one or more computer processors associated with the detected error. The one or more computers determine on which of the one or more computer processors the second counter is frozen. The one or more computers report a time-of-day network error, where reporting a time-of-day network error includes assigning a priority to one or more sources of the time-of-day network error.

A component mounting system includes a component mounting line in which a plurality of processing devices are connected to constitute the component mounting line and a management device (management computer) connected to the component mounting line by a network, and each of the plurality of processing devices can be remotely operated via the network by an input unit of the management device. In this component mounting system, it is determined whether or not an error occurring in the processing device is a remote response error (ST1), and notification in a first notification pattern is performed (ST2) in a case where a type of the error is the remote response error (Yes in ST1) and notification in a second notification pattern is performed (ST3) in a case where the type of the error is not the remote response error (No in ST1) based on a result of the error type determination.

Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.