A system for detecting errors and correcting errors in a multi-thread processor is disclosed. The multi-thread processor includes a first processor and a second processor. First processor executes a first thread and a second thread. Second processor executes a third thread and fourth thread. An instruction execution is initiated in all four threads. Output of the instruction execution from all four threads are compared for a match by a data compare engine to detect an error in execution of the instruction. When output of the instruction execution from one of the four threads does not match, an error in execution is detected and the output is replaced by one of the other three threads whose output does match. When output of the instruction execution by two or more threads does not match, error is detected, but not corrected.

A processor capable of changing redundant processing node comprises a plurality of processing nodes and a plurality of comparators. The plurality of processing nodes comprises a first processing node, a second processing node, and a third processing node, wherein the first processing node performs a first computation, the second processing node selectively performs the first computation or a second computation, and the third processing node performs the second computation. The plurality of comparators comprises a first comparator and a second comparator, wherein the first comparator connects to the first and second processing nodes to compare whether the results of the first computation performed by the first and second processing nodes are identical, and the second comparator connects to the second and third processing nodes to compare whether results of the second computation performed by the second and third processing nodes are identical.

An information processing apparatus that can perform error notification with ease and at a low cost in a case where falsification of an activation program is detected. The information processing apparatus has a main CPU for executing various programs, a sub CPU for verifying falsification of the activation program of the main CPU and perform recovery processing for the falsification, a FLASH Memory for storing a boot code of the activation program, a hardware sequencer for selectively switching one of the main CPU and the sub CPU so as to be capable of accessing the FLASH Memory, and a LED having three types of notification patterns. The hardware sequencer causes notification of the LED to change one of the three types of notification patterns according to both states of a falsification detection determination signal and an UNDER_RECOVERY signal from the sub CPU.

Discrete logic safety systems for smart process control devices are disclosed. A discrete logic safety system includes a heartbeat monitor to be operatively coupled to a processor of the process control device to monitor a first condition of the processor, a sensor monitor to be operatively coupled to a sensor of the process control device to monitor a second condition of the sensor, and first discrete logic operatively couple to the heartbeat monitor and the sensor monitor to generate a failure indication associated with the process control device based on the first condition or the second condition.

Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.

A storage device includes at least one nonvolatile memory device configured to store self-diagnosis firmware and a storage controller configured to communicate with an external device through a sideband interface. The storage controller is configured to perform self-diagnosis of the storage device using the self-diagnosis firmware according to the control of the external device. The storage controller is configured to transmit a result of the self-diagnosis to the external device through the sideband interface.

The present disclosure provides a method and a system of verifying access by a multi-core interconnect to an L2 cache in order to solve problems of delays and difficulties in locating errors and generating check expectation results. A consistency transmission monitoring circuitry detects, in real time, interactions among a multi-core interconnects system, all single-core processors, an L2 cache and a primary memory, and sends collected transmission information to an L2 cache expectation generator and a check circuitry. The L2 cache expectation generator obtains information from a global memory precise control circuitry according to a multi-core consistency protocol and generates an expected result. The check circuitry is responsible for comparing the expected result with an actual result, thus implementing determination of multi-core interconnect's access accuracy to the L2 cache without delay.

Embodiments of the present disclosure include an error recovery method comprising detecting a computing error, restarting a first artificial intelligence processor of a plurality of artificial intelligence processors processing a data set, and loading a model in the artificial intelligence processor, wherein the model corresponds to a same model processed by the plurality of artificial intelligence processors during a previous processing iteration by the plurality of artificial intelligence processors on data from the data set.

An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

An apparatus is described comprising a cluster of processing elements. The cluster having a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking correctness of a primary processing workload performed by the primary processing element. Each processing element has an associated local memory comprising a plurality of memory locations. A local memory access control mechanism is configured, during the lock mode, to allow the at least one primary processing element to access memory locations within the local memory associated with the at least one redundant processing element.