Patent classifications
G06F11/076
Bit error rate estimation and error correction and related systems, methods, devices
Physical layer devices and related methods for determining Bit Error Rates (BERs) and correcting errors in signals received through shared transmission media of wireless local area networks are disclosed. A physical layer device is configured to identify coding violations in received signal, determine a rate of the coding violations in the signal, and estimate a BER of the signal to be equal to the determined rate of the coding violations. A physical layer device is configured to invert a half symbol immediately preceding or immediately following a coding violation based, at least in part, on signal integrities of the half symbol immediately preceding and the half symbol immediately following the coding violation to correct a bit error.
Generation of an issue response analysis evaluation regarding a system aspect of a system
A method includes determining, by an analysis system, a system aspect of a system for an issue response analysis evaluation. The method further includes determining, by the analysis system, at least one evaluation perspective and at least one evaluation viewpoint for use in performing the issue response analysis evaluation on the system aspect. The method further includes obtaining, by the analysis system, issue response analysis data regarding the system aspect in accordance with the at least one evaluation perspective and the at least one evaluation viewpoint. The method further includes calculating, by the analysis system, an issue response analysis rating as a measure of system issue response analysis maturity for the system aspect based on the issue response analysis data, the at least one evaluation perspective, the at least one evaluation viewpoint, and at least one evaluation rating metric.
Modifying conditions for memory device error corrections operations
In response to a determination that an error rating condition associated with a memory device is satisfied, a first error correction operation is performed at the memory device to correct one or more first errors associated with a first memory access operation at the memory device. A detection is made that at least one of a state of the memory device has changed from a first state to a second state or a behavior of the memory device has changed from a first behavior level to a second behavior level. The error rating condition is modified in view of the at least one of the second state of the memory device or the second behavior level of the memory device. In response to a determination that the modified error rating condition is satisfied, a second error correction operation is performed at the memory device to correct one or more second errors associated with a second memory access operation performed at the memory device.
Read voltage calibration for copyback operation
A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.
Techniques for command execution using a state machine
Techniques for processing a request may include: providing tasks to a state machine framework, wherein the tasks perform processing of a workflow for servicing the request; generating, by the state machine framework, a state machine for processing the request, wherein the state machine includes states associated with the tasks, wherein generating the state machine may include automatically determining a first state transition of the state machine between a first and a second of the states; receiving the request; and responsive to receiving the request, performing first processing using the state machine to service the request. The framework may automatically generate triggers that drive the state machine to determine subsequent states in accordance with defined state transitions. State machine internal state information may be persistently stored and used in restoring the state machine to one of its states in connection processing of the command.
IDENTIFYING AND COLLECTING DATA FROM ASSETS OF A SYSTEM UNDER EVALUATION BY A SYSTEM ANALYSIS SYSTEM
An analysis system determines a system aspect of a system, determines an evaluation perspective for use in performing an asset management evaluation on the system aspect relating to a build of the system, an evaluation viewpoint corresponding to discovered information of the system and selects a plurality of data structures identifying data to be collected based thereupon. The analysis system, based upon the system aspect, the evaluation perspective, the evaluation viewpoint, and the plurality of data structures, determining context data. Based upon the plurality of data structures, the analysis system identifies a plurality of physical assets of the system for collection of data, queries the plurality of physical assets of the system to collect data to populate the plurality of data structures. The analysis system evaluates the data structures using the context data to produce an evaluation of at least some of the plurality of physical assets of the system.
Information processing device, external storage device, host device, relay device, control program, and control method of information processing device
According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device.
Using erasure coding across multiple regions to reduce the likelihood of losing objects maintained in cloud object storage
Techniques for using erasure coding across multiple regions to reduce the likelihood of losing objects in a cloud object storage platform are provided. In one set of embodiments, a computer system can upload each of a plurality of data objects to each of a plurality of regions of the cloud object storage platform. The computer system can further compute a parity object based on the plurality of data objects, where the parity object encodes parity information for the plurality of data objects. The computer system can then upload the parity object to another region of the cloud object storage platform different from the plurality of regions.
CROSSING FRAMES ENCODING MANAGEMENT METHOD, MEMORY STORAGE APPARATUS AND MEMORY CONTROL CIRCUIT UNIT
A crossing frames encoding management method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: reading a tag swap information corresponding to a first physical group; encoding a first data; storing a first part of the encoded first data to at least one first physical unit corresponding to a first tag information in the first physical group; and storing a second part of the encoded first data to at least one second physical unit corresponding to a second tag information in the first physical group according to the tag swap information. The first tag information corresponds to a first crossing frames encoding group. The second tag information corresponds to a second crossing frames encoding group. The first crossing frames encoding group is different from the second crossing frames encoding group.
Secure-Erase Prediction for Data Storage Devices
Systems and methods for predicting whether a nonvolatile memory block is likely capable of being securely erased to be eligible for composing into another composable infrastructure are described. A management module receives a secure-erase command to erase at least one nonvolatile memory block, determines health parameters of the nonvolatile memory block, calculates a failure index based on the health parameters, and, based on the failure index, either securely erases the block of memory or retires the nonvolatile memory block.