Techniques are disclosed relating to methods that include initializing, by a computer in a computer system, an event counter that includes a plurality of sub-counter groups, each plurality of sub-counter groups including at least two sub-counters located on different nodes of a plurality of nodes in the computer system. In response to an occurrence of an event associated with the event counter, the method may include the computer selecting a particular sub-counter group of the plurality of sub-counter groups to update, and sending, to sub-counters corresponding to the particular sub-counter group, a request to update a sub-counter value for the particular sub-counter group. In response to a request for a current count value of the event counter, the method may include outputting, by the computer, a sum of the sub-counter values for the plurality of sub-counter groups as the current count value.

A method and apparatus for enhancing reliability of a data storage device. The storage device controller is configured to convert a typical UBER-type event to an MTBF (FFR) event by converting a data error event into a drive functional failure. In this context, the converted error is not counted as an UBER type event for purposes of determining the reliability of the storage device.

In some examples, a system records, in a data structure stored in a non-volatile storage, information of memory errors in respective segments of a memory. The system determines whether memory errors of a subset of the segments satisfy a criterion, and in response to determining that the memory errors of the subset of the segments satisfy the criterion, the system groups the memory errors of the subset into a partition having a size greater than a size of a segment. The system records, in the data structure, information of memory errors in the partition, and in response to a restart of the system, retrieves the data structure from the non-volatile storage for use in an operation that addresses memory errors in the system.

A method for striping based on evaluated rules, the method may include determining a compatibility, with a storage system utilization policy, of storing stripes under evaluated rules; wherein the evaluated rules define a stripe size, a number of parity chunks per stripe, and maximal numbers of chunks within a stripe per different failure domains of different size ranges; checking whether the storing of the stripes is compatible with the storage system utilization policy; when finding that the storing of the stripes is not compatible then searching for one or more changes of one or more of the maximal numbers that yields compliant one or more maximal numbers that once applied results in a compliance with the storage system utilization policy; applying the compliant one or more maximal numbers when finding the compliant one or more maximal numbers; and determining that the evaluated failure domain rules are non-compliant when failing to find the compliant one or more maximal numbers.

An average inter-pulse delay of a data unit of the memory device is calculated. An average temperature of the data unit is calculated. A first scaling factor based on the average inter-pulse delay and a second scaling factor based on the average temperature is obtained. A media management metric based on the first scaling factor and the second scaling factor is calculated. Responsive to determining that the media management metric satisfies a media management criterion, a media management operation on the data unit at a predetermined cycle count is performed.

A system includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing, during chip initialization, a first attempt of a chip initialization process to be performed based on a first configuration. The first configuration includes a first set of control settings for reading a block of the memory array during the first attempt. The operations further include determining that the first attempt has failed, and, in response to determining that the first attempt has failed, causing an automatic chip initialization retry process to be performed. Causing the automatic chip initialization retry process to be performed includes causing a second attempt of the chip initialization process to be performed using a second configuration. The second configuration includes a second set of control settings different from the first set of control settings for reading the block during the second attempt.

A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.

An error rate measuring apparatus detects a bit error of input data returned from a device under test with transmission of a test signal at an error detector, and includes a log recording unit that records log data of state transition of each lane by handshakes of a plurality of lanes in a predetermined communication standard with respect to the device under test in making the device under test transit to a state of LOOPBACK, and a display unit that displays the recorded log data of the state transition of each lane in a time-series order.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with multiple hardware devices of the IHS. The BMC includes executable instructions for monitoring a parameter of one or more of the hardware devices when a custom BMC firmware stack is executed on the BMC. The instructions that monitor the parameter are separate and distinct from the instructions of the custom BMC firmware stack. The instructions also control the BMC to perform one or more operations to remediate an excessive parameter when the parameter exceeds a specified threshold.