A method for performing error correction for a plurality of storage drives and a storage appliance comprising a plurality of storage devices is disclosed. In one embodiment, the method includes generating a first set of parity bits from a first set of data of at least one of the plurality of storage devices, the first set of parity bits capable of correcting a first number of error bits of the first set of data. The method further includes generating a second set of parity bits from a concatenated set of the first data and a second set of data from at least another of the plurality of storage devices, the second set of parity bits capable of correcting a second number of error bits of the first set of data, the second number being greater than the first number. The method further includes reading the first set of data and (i) correcting error bits within the first set of data with the first set of parity bits where a number of error bits is less than the first number of error bits; and (ii) correcting error bits within the first set of data with the second set of parity bits where the number of error bits is greater than the first number.

Devices, systems and methods for improving reliability and security of a memory system are described. An example method includes receiving a seed value and a data stream, generating, based on the seed and using a physical unclonable function (PUF) generator, a PUF data pattern, generating, based on the seed, a pseudo-random data pattern, performing a first logic operation on the PUF data pattern and the data stream to generate a result of the first logic operation as a first data sequence, and performing a second logic operation on the pseudo-random data pattern and a second data sequence that is based on the first data sequence to generate a result of the second logic operation as a third data sequence for storage on the memory system, wherein the PUF generator is selected at least in-part based on one or more physical characteristics of the memory system.

A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate an estimated codeword based on a result of hard decoding the first codeword and a result of hard decoding a second codeword. The circuit may be further configured to generate soft information based on the hard decoding result of the first codeword and the estimated codeword. The circuit may be further configured to decode the result of the read operation on the flash memory using the soft information.

A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.

Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.

The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.

A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit.

Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.