A system receives, via a graphical user interface (GUI), a user selection of one or more parameters indicative of a request to segment the memory device into partitions for use by a host system. Responsive to receiving, via the GUI, the user selection of the one or more parameters indicative of the request to segment the memory device into the partitions, the system configures a first partition of the partitions with one or more configuration settings based on the one or more parameters. To configure the first partition, the system determines a memory type from multiple memory types based on the one or more parameters, and configures the first partition of the partitions to operate as the determined memory type.

Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

One or more parameters indicative of a request to segment the memory device into multiple partitions for use by a host system are received. Responsive to receiving the one or more parameters indicative of the request to segment the memory device into multiple partitions, a first partition is configured with one or more configuration settings based on the one or more parameters. Configuring the first partition includes determining a memory type from multiple memory types based on the one or more parameters, and configuring the first partition to operate as the determined memory type. The memory types define a number of bits that a memory cell of the first partition is to store.

An image processing apparatus including a plurality of transfer units, a data storage, an image processing processor, and a test circuit. A plurality of captured image data are respectively assigned to the plurality of transfer units and the plurality of transfer units transfer the assigned image data. The data storage unit stores the plurality of image data which are transferred by the plurality of transfer units. The image processing processor performs image processing on the plurality of image data which are stored in the data storage unit. The test circuit tests the image processing processor in a period during which the image data are not input from the data storage unit to the image processing processor.

Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.

Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

A system is provided to receive a request to write data to a storage device, wherein the data is associated with a file name and a file path. The system performs a hash function on an input based on the file name and the file path to obtain a hash value, wherein the hash function comprises a plurality of hash methods performed on the input. The system maps the hash value to a physical location in the storage device, and writes the data to the physical location in the storage device.

A storage client needs to store to-be-written data into a distributed storage system, and storage nodes corresponding to a first data unit assigned for the to-be-written data by a management server are only some nodes in a storage node group. When receiving a status of the first data unit returned by the management server, the storage client may determine quantities of data blocks and parity blocks needing to be generated during EC coding on the to-be-written data. The storage client stores the generated data blocks and parity blocks into some storage nodes designated by the management server in a partition where the first data unit is located. Accordingly, dynamic adjustment of an EC redundancy ratio is implemented, and the management server may exclude some nodes in the partition from a storage range of the to-be-written data based on a requirement, thereby reducing a data storage IO amount.

In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.

Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.