A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.

A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.

For NAND devices having a zero voltage program state as a result of a preconditioning operation, detecting the status of the zero voltage program state is important for customers to quickly validate their component and SSD flows to improve NAND retention and reliability after assembly and die level re-work. A zero voltage program state detection operation quickly determines the validity of the zero voltage program state of a NAND page of a NAND device. The detection operation includes reading a NAND page with reference voltages that delimit a predetermined acceptable range of voltage levels below and above a zero threshold voltage. If NAND memory cells having threshold voltage levels that fall below or above the acceptable voltage levels exceed a predetermined failed bytes limit for the NAND page, the zero voltage program state is invalid.

A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

A memory system and a memory controller are disclosed. By determining whether an error has occurred in target data stored in a predetermined target memory area of the memory device and determining, in response to whether an error has occurred in the target data, the magnitude of the supplied power based on a first operation parameter selected among predetermined candidate operation parameters in connection with the magnitude of the supplied power, the memory controller may stably drive a firmware, and may handle an operation error of the firmware due to a change in external environment.

Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

A memory sub-system configured to read soft bit data by adjusting the read voltage applied to read hard bit data from memory cells. For example, in response to a read command identifying a group of memory cells, a memory device is to: read the group of memory cells using a first voltage to generate hard bit data indicating statuses of the memory cells subjected to the first voltage; change (e.g., through boosted modulation) the first voltage, currently being applied to the group of memory cells, to a second voltage and then to a third voltage; reading the group of memory cells at the second voltage and at the third voltage to generate soft bit data (e.g., via an exclusive or (XOR) of the results of reading the group of memory cells at the second voltage and at the third voltage).

Systems and methods are disclosed, including rebuilding a logical-to-physical (L2P) data structure of a storage system subsequent to relocating assigned marginal group of memory cells of a memory array of the storage system, such as when resuming operation from a low-power state, including an asynchronous power loss (APL).