Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.

Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

Memory with address-selectable data poisoning circuitry is disclosed herein. In one embodiment, a memory device comprises circuitry operably connected to a memory array. The circuitry can include memory row address registers and/or memory column address registers. Standard access commands or mode register write commands can be used to load a memory row address or a memory column address into the memory row address registers or the memory column address registers, respectively. During a read operation directed to a second memory row and/or column of the memory array, the circuitry can compare the second memory row to the first memory row and/or the second memory column to the first memory column, and can poison a data bit read from the memory array before the data bit is output from the memory device when the first and second memory row addresses match and/or when the first and second memory column addresses match.

Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.

Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

An approach for reducing disturbed errors in a flash memory device is disclosed. The approach includes collecting information associated with one or more; determining one or more frequently accessed data blocks from the one or more blocks based on the collected information; determining one or more neighboring blocks from the one or more blocks based on the collected information; determining if the one or more neighboring blocks exceeds a disturbance threshold; and in responsive to the one or more neighboring blocks has exceeded the disturbance threshold, re-align the one or more blocks.

Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.

A storage device detects an error of ROM data and corrects the error. The storage device includes a memory device and a memory controller for controlling the memory device. The memory device includes a plurality of planes each storing Read Only Memory (ROM) data, and a ROM data controller configured to control the plurality of planes based on whether the ROM data from all of the planes are the same. The memory controller includes an operation state determiner configured to output to the ROM data controller a ROM data output command for reading the ROM data respectively stored in the plurality of planes, according to an operation state of the memory device.

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

The present invention relates to computerized (“smart”) mobile electronic devices and more particularly, to a system and methods of diagnosing and repairing malfunctions in smart mobile electronic devices, including a diagnostic process that utilizes decisions based on Big Data that holds information of multiple devices and offers a “disable components” (i.e., turn-off components) solution in order to overcome the problem without flashing a firmware or doing a factory-reset.