A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.

An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table. The processor can also include processor core coupled to the memory. The processor core can receive, from an application, a memory access request to access data of one or more contiguous memory blocks in a memory object of the memory. The processor core can also retrieve data stored in the one or more contiguous memory blocks based on the location indicated by the pointer. The processor core can also retrieve, from the MCD table, allocation information associated with the one or more contiguous memory blocks. The processor core can also send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information.

A ternary content addressable memory (TCAM) is disclosed. The TCAM includes a memory array, a data match module, and compare circuitry. The memory array stores a data entry for a data word and a corresponding duplicate data entry for the data word. The data match module compares the data entry to an input word to produce a first match output, and compares the duplicate data entry to the input word to produce a second match output. The compare circuitry compares the first match output and the second match output.

Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

An apparatus comprises a non-associative memory comprising a plurality of storage locations, and error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory. Control circuitry is responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in the valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address. This enables the apparatus to continue to function even if hard errors occur in a storage location of the non-associative memory.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

A method of correcting errors in a data storage system including a first node, a second node, and shared persistent storage (the first and second nodes being configured to process data storage requests) is provided. The method includes (a) reading cached pages from a first cache disposed within the first node, the cached pages being cached versions of respective persistent pages stored in the shared persistent storage; (b) in response to determining that one of the cached pages is corrupted, requesting that the second node return to the first node a corresponding remote page from a second cache disposed within the second node, the cached page and the remote page each caching a same persistent page of the shared persistent storage; and (c) in response to determining that the remote page received from the second node by the first node is not corrupted, correcting the cached page using the remote page.

Systems and methods for recovering corrupted data or missing data from a cache are provided. When a data corruption is discovered in a storage system, the cache may be searched to determine if a valid copy of the corrupted data can be recovered from the cache.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.