An error recovery process provides for selecting a first recovery scheme for a decoding attempt on a first subset of a set of failed data blocks read from a data track; selecting a second different recovery scheme for a decoding attempt on a second subset of the set of failed data blocks read from the data track; and during a single revolution of the data track, performing operations to decode a first subset of the failed data blocks according to the first recovery scheme operations to decode the second subset of the failed data blocks according to the second different recovery scheme.

A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A value of the first read voltages is selected based on error correction coding (ECC) related information related to the multiple representations of the data. In another embodiment, storage elements of the memory are sensed using a set of candidate read voltages to generate sensing data that is transferred to a memory accessible to the controller. The multiple representations of data may be generated based on the sensing data to emulate results of reading the storage elements using a different combination of candidate reading voltages.

Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect.

A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.

A processor includes at least one memory controller, and a decode unit to decode a persistent commit demarcate instruction. The persistent commit demarcate instruction is to indicate a destination storage location. The processor also includes an execution unit coupled with the decode unit and the at least one memory controller. The execution unit, in response to the persistent commit demarcate instruction, is to store a demarcation value in the destination storage location. The demarcation value may demarcate at least all first store to persistent memory operations that are to have been accepted to memory when the persistent commit demarcate instruction is performed, but which are not necessarily to have been stored persistently, from at least all second store to persistent memory operations that are not yet to have been accepted to memory when the persistent commit demarcate instruction is performed.

There are provided a memory system and a method for operating the same. A memory system includes: a controller for queuing a plurality of commands and outputting control signals in response to the plurality of queued commands; and a memory device for performing a program operation in response to the control signals, wherein, when the program operation fails, the controller holds the plurality of queued commands.

A data processing method, an electronic device and a non-volatile storage medium are disclosed, the method includes selecting a next to be executed thread and determining whether the selected thread is a high-performance thread. If the selected thread is a high-performance thread and a thread-user of the on-chip memory is not the selected high-performance thread, contents of the on-chip memory are backed to a stack memory of a thread corresponding to the thread-user. Contents of a stack memory of the selected thread are backed to the on-chip memory. The thread-user of the on-chip memory is updated to indicate the selected thread. The contents of the on-chip memory in a CPU register is stored to complete the switching out; and the selected thread is executed. The present disclosure can accelerate and speed up data processing.