A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Embodiments of this disclosure are directed towards a method of logging messages in a baseboard management controller (BMC) system. The method includes powering on a processing chip of the BMC system, wherein the processing chip has a main processor and a co-processor that is communicatively coupled to a non-transitory processor-readable memory device and snooping interface. The method further includes booting up the co-processor, and initiating a storage portion of the non-transitory processor-readable memory device the snooping interface. The method further includes triggering a boot-up of the main processor, and receiving, via the snooping interface, the messages redirected from a communication interface of the BMC system.

The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

A slave provides second data bits and ECC bits in response to a master read request. First data bits are generated by selecting between the second data bits and third data bits produced from error correcting the second data bits. The third data bits are generated with a delay of one clock cycle with respect to the second data bits. If an address of the read request is stored to a memory, a control signal is set indicating that the first data bits are invalid and this drives selection of the third data bits (with the first data bits now being valid in a following clock cycle). If an error signal is asserted when the address is not stored to the memory, action is taken to store the address to the memory and a further control signal is set to indicate that the read request should be repeated.

An integrated circuit (IC) includes a memory that stores a thread and a processor that generates an instruction request to retrieve one or more instructions of the thread. The IC further includes an error control circuit that receives the instruction request from the processor and retrieves an instruction of the thread from the memory based on the instruction request. Further, the error control circuit determines whether the retrieved instruction is erroneous. Based on the determination that the retrieved instruction is erroneous, the error control circuit provides a substitute instruction to the processor as a response to the instruction request. The substitute instruction is included in an instruction set of the processor. The processor executes the received substitute instruction and suspends an execution of the thread.

Embodiments are generally directed apparatuses, methods, techniques and so forth determine an access level of operation based on an indication received via one or more network links from a pod management controller, and enable or disable a firmware update capability for a firmware device based on the access level of operation, the firmware update capability to change firmware for the firmware device. Embodiments may also include determining one or more configuration settings of a plurality of configuration settings to enable for configuration based on the access level of operation, and enable configuration of the one or more configuration settings.

A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

An error associated with a read operation corresponding to a memory die of a memory subsystem is detected. In response to detecting the error, a first read throughput level of the memory subsystem is identified. A quantity of queues receiving operation requests is decreased, the decreased quantity of queues corresponding to a second read throughput level. A read retry operation associated with the memory die is initiated at the second read throughput level.

A processing device includes: a first processor configured to execute a determination process; and a second processor configured to communicate with the first processor via an internal bus, wherein the determination process includes processes of determining that the abnormality occurs inside the processing device when first reference data transmitted to the second processor and first diagnostic data that is response data to the first reference data do not correspond to each other, and determining that the abnormality occurs in at least one of an external bus or an external device when the first reference data and the first diagnostic data correspond to each other and second reference data transmitted to the external device and second diagnostic data that is response data to the second reference data do not correspond to each other.

Provided is a method for detecting stored data and device, a storage medium and an electronic device. The method includes: the first check information of first data stored in a memory in the current period is determined; the first check information is compared with second check information to obtain a check result, wherein the second check information is check information of second data stored in the memory in a period prior to the current period; and the correctness of storage of the second data is detected according to the check result.