A method for determining the integrity of navigation data of a control unit of an automotive vehicle, including the steps involving setting two counters to a value strictly above the maximum of the two counters, and, in a waking phase, calculating the fingerprints of the data written to the reset safe area, comparing the counters and determining the integrity of the data when the counters are the same.

A peripheral device includes a bus interface and circuitry. The bus interface is configured to connect to a peripheral bus for communicating with a host in accordance with a peripheral-bus specification that specifies a physical reset signal asserted by the host. The circuitry is configured to execute predefined logic that evaluates a reset condition that is indicative of imminent assertion of the physical reset signal by the host, and to perform a reset procedure in response to meeting the reset condition.

A method may include determining whether a fault has occurred in connection with a distribution unit for a fluidic network. The method may also include operating a plurality of three-way valves in a normal mode of operation in absence of the fault, wherein in the normal mode, the coolant fluid flows in parallel through the heat exchanger and the fluidic network. The method may also include operating the plurality of three-way valves in a failure mode in response to the fault, wherein in the failure mode, the coolant fluid flows in serial through the heat exchanger, then the fluidic network.

A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

The invention relates to a data processing system and a date processing method. The data processing system is configured to perform a hardware transactional memory (HTM) transaction. The data processing system comprises a byte-addressable nonvolatile memory for persistently storing data and a processor being configured to execute an atomic HTM write operation in connection with committing the HTM transaction by writing an indicator to the nonvolatile memory indicating the successful commit of the HTM transaction.

In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

A warm mission-mode reset may be performed in a portable computing device. Assertion of a signal indicating an error condition may be detected. In response to detection of the signal indicating an error condition, a signal indicating a request to preserve memory contents may be provided to a DRAM subsystem. Then, in response to a signal acknowledging the DRAM subsystem is preserving the memory contents, a system reset signal may be asserted.

Data may be transferred from a volatile memory to a non-volatile memory using a persistent power enabled on-chip data processor upon detecting a power loss from a primary power source. The one or more emergency power supplies are attached to the volatile memory, the non-volatile memory, and the persistent power enabled on-chip data processor to assist with the transferring of data.

A multi-screen display control device includes a plurality of graphics processing units (GPUs) and a watchdog chip. The GPUs transform image data that a host transfers to the multi-screen display control device through a universal serial bus (USB) interface into a plurality of high-definition multi-media interface (HDMI) sub-images to be displayed by a plurality of screens. The watchdog chip is coupled to the GPUs and, when any of the GPUs crashes, the watchdog chip outputs a reset signal to reset all of the GPUs.