An improved blockchain implementation that uses proof-of-transfer to overcome the technical deficiencies of proof of work and proof-of-stake implementations is described herein. For example, the proof-of-transfer process may include elements of a single-leader election sortition, but modified to cause base chain cryptocurrency committed for the purposes of the sortition to be transferred to a burn address or at least one reward address.

An output determination circuit is fabricated by a hard-wired scheme to execute an instruction via hardware connection. The output determination circuit determines an output signal of a Field Programmable Gate Array (FPGA) which operates according to logic information. The output determination circuit comprises a majority decision circuit. The majority decision circuit is connected to outputs of a plurality of FPGAs which perform the same operation. The majority decision circuit performs majority decision on the outputs of the plurality of FPGAs to determine outputs from the plurality of FPGAs as an output signal. The majority decision circuit is constituted of only logic operation elements.

A redundancy method of a three-dimensional laminated memory includes receiving, by first, second and third processors, a command for data operation, transmitting and receiving, by each of the second and third processors, data through dedicated data buses in order to perform the data operation, receiving, by the first processor, operation result values of the second and third processors from a main memory, comparing, by a result value comparator of the first processor, the operation result values of the first, second and third processors, and outputting, by the result value comparator, operation result values in correspondence with the result of comparison.

This application relates to a shared data recovery method performed at a first node of a data sharing system. The first node obtains a first eigenvalue of a first node after receiving a recovery request carrying a first block height; broadcasts the first eigenvalue to at least one second node and recovery indication information to the at least one second node. After determining, based on the first eigenvalue and a plurality of second eigenvalues, that data in shared data stored by all nodes of the data sharing system is consistent, the first node recovers data within a range of the first block height in the shared data after receiving a preset quantity of a plurality of pieces of recovery indication information, thereby ensuring consistency and security of data included in a block, and reducing pressure on a node of the data sharing system to store the shared data.

A method for operating a controlled object that is embedded in a changing environment. The controlled object and its environment are periodically observed using sensors. Independent data flow paths (DFP) are executed based on the data recorded through the observation of the controlled object and its environment. A first DFP determines a model of the controlled object and the environment of the controlled object and carries out a trajectory planning in order to create possible trajectories that, under the given environmental conditions, correspond to a specified task assignment. A second DFP determines a model of the controlled object and of the environment of the controlled object and determines a safe space-time domain (SRZD) in which all safe trajectories must be located. The results of the first and the second DFP are transmitted to a deciding instance to verify whether at least one of the trajectories is safe.

Disclosed is a high data integrity processing system (HDIPS) that includes a first processing device and a triple voted processing (TVP) device in signal communication with the first processing device. The first processing device has a high radiation resistance and includes a processor, a cache memory, and a computer-readable medium (CRM). The CRM has encoded thereon computer-executable instructions to cause the processer to execute a periodic first integrity check on the first processing device producing a first integrity result, which is transmitted to the TVP device. The TVP device includes firmware having encoded thereon machine instructions to, simultaneously with the periodic first integrity check, cause the TVP device to execute a second integrity check producing a second integrity result, compare the first integrity result with the second integrity result, and power reset the first processing device if the first integrity result does not match the second integrity result.

An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.

A high availability scheduler of tasks in a cluster of server devices is provided. A server device of the cluster of server devices enters a leader state based upon the results of an election process in which the server device participates with others of the cluster of server devices. Upon entering the leader state, the server device schedules one or more tasks by assigning each of the one or more tasks to a device, wherein the one or more tasks involve initiating a search of time stamped events.

A redundancy method of a three-dimensional laminated memory includes receiving, by first, second and third processors, a command for data operation, transmitting and receiving, by each of the second and third processors, data through dedicated data buses in order to perform the data operation, receiving, by the first processor, operation result values of the second and third processors from a main memory, comparing, by a result value comparator of the first processor, the operation result values of the first, second and third processors, and outputting, by the result value comparator, operation result values in correspondence with the result of comparison.

There is disclosed a computing/data processing device comprising: a plurality of computing units, each computing unit comprising a computing resource; the computing device comprising at least three computing units, each computing unit comprising a/the same computing resource; each computing unit further comprising a computing unit access manager, each unit access manager being adapted to control access to the computing resource of the respective computing unit in response to at least one request; wherein, the computing unit access manager only allows a response to the at least one request if a majority of the computing units provide a same response to the at least one request; and wherein, the computing device comprising a network-on-a-chip, is provided on a chip and/or comprises an integrated chip (IC) or microprocessor. The IC beneficially comprises a Field-Programmable Gate Array (FPGA) device. In a preferred embodiment, the unit access manager controls access to the computing resource based on a token; the token comprising: a pointer to the respective computing resource, a set of rights relating to that computing resource, and a numerical representation of that computing resource.