A method for performing initial registration is provided. The method includes receiving a server timeout message, the server timeout message including at least a field set to a value equal to a value received during a first registration. The method further includes initiating restoration procedures by performing an initial registration.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

A method for transmitting data between functions implemented on a first electronic chip of the manycore type. The first electronic chip includes a plurality of execution cores, the execution cores being grouped in clusters, the clusters being interconnected by at least two communication systems. The data transmission method includes the steps of: implementing a first function on a first cluster; implementing a second function on a second cluster, characterised in that the second function is also implemented on a third cluster distinct from the first and second clusters; and transmitting at least one data item between the first function and the second function.

A retimer includes a first port to couple to a die over a first interconnect, where the first interconnect includes a defined set of lanes and utilizes a first communication technology, and the die is located on a first package with the retimer. The retimer further includes a second port to couple to another retimer over a second interconnect, where the second interconnect utilizes a different second communication technology, and the second retimer is located on a different, second package to facilitate a longer reach communication channel.

In one embodiment, a computer networking device calculates a first hash value for an identifier of a group of computing devices, as well as a second hash value for the identifier of the group of computing devices, with each hash value being at least in part on the identifier of the group of computing devices and an identifier of the respective interface. The computer networking device may also analyze the first hash value with respect to the second hash value and select the first interface for association with the identifier of the group of computing devices based at in part on the analyzing. The computer networking device may further store an indication that the identifier of the group of computing devices is associated with the first interface.

Apparatus and methods for flexible input/output signaling over a same signaling channel are described. A programmable interface circuit includes a signaling channel that can be adapted, prior to use or during operation, for transmission and/or reception of different types of analog and digital signals. The interface circuit can be used for communications between an isolating communication controller and components of a machine that use diverse signaling types.

A host computing device includes a host processor, host memory in electronic communication with the host processor, and an auxiliary service controller. The host computing device also includes a communication interface and a messaging interface between the host processor and the auxiliary service controller. A message handler is stored in the host memory. The message handler is executable by the host processor in response to detecting a messaging interface signal on the messaging interface. Execution of the message handler by the host processor causes a firmware update patch to be read from a shared memory region in the auxiliary service controller via the communication interface.

Techniques are described for providing managed computer networks, such as for managed virtual computer networks overlaid on one or more other underlying computer networks. In some situations, the techniques include facilitating replication of a primary computing node that is actively participating in a managed computer network, such as by maintaining one or more other computing nodes in the managed computer network as replicas, and using such replica computing nodes in various manners. For example, a particular managed virtual computer network may span multiple broadcast domains of an underlying computer network, and a particular primary computing node and a corresponding remote replica computing node of the managed virtual computer network may be implemented in distinct broadcast domains of the underlying computer network, with the replica computing node being used to transparently replace the primary computing node in the virtual computer network if the primary computing node becomes unavailable.

A workgroup-computing-entity-based fail-safe/evolvable hardware core structure is disclosed which includes a 3-hierarchical-level 6-workgroup-Basic-Building-Block (6-wBBB) created to supplant the node-computing-entity-based non-fail-safe/limited evolvable von-Neumann core structure of 3-hierarchical-level 3-node-BBB, (i.e., base-level JO-devices/mid-level main memory/top-level CPU) and all the first-time fail-safe workgroup systems can be subsequently generated in the second period along the workgroup-computing evolutionary timeline. Furthermore, based on the first 6-wBBB evolvable architecture, the workgroup evolutionary processes can go up to 7 generations in creating all the necessary workgroup-computing entity-based hardware core structures, so that all the real-time intelligent workgroup-computing systems can be generated in the third period along the workgroup-computing evolutionary timeline.

Described is a differential data bus system which maintains error free communication despite faults in one of the data bus lines.