Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

A system to which the present invention has been applied includes a plurality of information processing apparatuses connected to each other and a management device that divides a first number of pieces of management data needed for management of the plurality of information processing apparatuses into a second number of pieces of management data, the second number being equal to or greater than the first number, and that transmits the second number of pieces of management data obtained by the division respectively to the plurality of information processing apparatuses.

A method implemented by computer for compressing and decompressing all the fault scenarios of a processor comprising computation units interconnected by a communication network having topology symmetries, each fault scenario corresponding to the number and the location of one or more failing computation units and the method comprises the steps of reception or determination of one or more topology symmetries; determination of the equivalent scenarios by means of said topology symmetries; each of the fault equivalence classes being associated with a resource allocation solution in terms of mapping and routing. Different developments include the determination or the application of an inference engine, of identifiers associated with the fault scenarios, of combinatorial exploration techniques, of compression rates, of reconfiguration of the processor and of classification of the processor in a range. A program product and associated systems are also described.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.

A system can receive an untrusted onboard announcement message from a remote computer, wherein the untrusted onboard announcement message comprises first data that identifies the remote computer and second data that indicates a current configuration of the remote computer. The system can identify a stored indication of an authorized configuration of the remote computer based on the data that identifies the remote computer. The system can determine that there is a mismatch between the authorized configuration of the remote computer and the current configuration of the remote computer. The system can determine a trust metrics evaluation score for the remote computer based on a type of hardware component change between the authorized configuration of the remote computer and the current configuration of the remote computer. The system can, in response to determining that the trust metrics evaluation score is greater than a threshold value, onboard the remote computer.

A system that includes a graphics processing unit (GPU) that includes: at least one processor and circuitry to: based on failure of the GPU to load boot firmware, operate as a survivability agent to allow for the GPU to boot to a configuration wherein a host system is to communicate with the GPU to determine the failure of the GPU to load boot firmware and to load second boot firmware for access by the GPU. In some examples, the GPU includes an input output (IO) subsystem and to boot to the configuration, the circuitry is to provide the host system with access to an indicator of failure of the GPU and access to the host system to load the second boot firmware into a boot storage accessible to the GPU.